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16-Bit, 160 MSPS 2x/4x/8x Interpolating Dual TxDAC+(R) D/A Converter AD9777
FEATURES
16-bit resolution, 160 MSPS/400 MSPS input/output data rate Selectable 2x/4x/8x interpolating filter Programmable channel gain and offset adjustment fS/4, fS/8 digital quadrature modulation capability Direct IF transmission mode for 70 MHz + IFs Enables image rejection architecture Fully compatible SPI port Excellent AC performance SFDR -73 dBc @ 2 MHz to 35 MHz WCDMA ACPR 71 dB @ IF = 19.2 MHz Internal PLL clock multiplier Selectable internal clock divider Versatile clock input Differential/single-ended sine wave or TTL/CMOS/LVPECL compatible Versatile input data interface Twos complement/straight binary data coding Dual-port or single-port interleaved input data Single 3.3 V supply operation Power dissipation: typical 1.2 W @ 3.3 V On-chip 1.2 V reference 80-lead thermally enhanced TQFP package
APPLICATIONS
Communications Analog quadrature modulation architecture 3G, multicarrier GSM, TDMA, CDMA systems Broadband wireless, point-to-point microwave radios Instrumentation/ATE
GENERAL DESCRIPTION
The AD97771 is the 16-bit member of the AD977x pin compatible, high performance, programmable 2x/4x/8x interpolating TxDAC+ family. The AD977x family features a serial port interface (SPI) that provides a high level of programmability, thus allowing for enhanced system level options. These options include selectable 2x/4x/8x interpolation filters; fS/2, fS/4, or fS/8 digital quadrature modulation with image rejection; a direct IF mode; programmable channel gain and offset control; programmable internal clock divider; straight binary or twos complement data interface; and a single-port or dual-port data interface.
(continued on Page 4)
1
Protected by U.S. Patent Numbers, 5,568,145; 5,689,257; and 5,703,519. Other patents pending.
FUNCTIONAL BLOCK DIAGRAM
IDAC COS
AD9777
HALFBAND FILTER1* 16 16 HALFBAND FILTER2* 16 HALFBAND FILTER3*
GAIN DAC SIN IMAGE REJECTION/ DUAL DAC MODE BYPASS MUX
OFFSET DAC
DATA ASSEMBLER 16 I AND Q NONINTERLEAVED OR INTERLEAVED DATA 16 I LATCH
fDAC/2, 4, 8
SIN
Q LATCH
16
16
16
16
WRITE SELECT
MUX CONTROL CLOCK OUT
FILTER BYPASS MUX /2 (fDAC) /2 /2 /2
COS IDAC IOUT
SPI INTERFACE AND CONTROL REGISTERS
PRESCALER
VREF
16
I/Q DAC GAIN/OFFSET REGISTERS
DIFFERENTIAL CLK
PLL CLOCK MULTIPLIER AND CLOCK DIVIDER
Figure 1.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
02706-B-001
* HALF-BAND FILTERS ALSO CAN BE CONFIGURED FOR "ZERO STUFFING ONLY"
PHASE DETECTOR AND VCO
IOFFSET
AD9777 TABLE OF CONTENTS
General Description ......................................................................... 4 Products Highlights ..................................................................... 4 Specifications..................................................................................... 5 Absolute Maximum Ratings............................................................ 9 Thermal Characteristics .............................................................. 9 ESD Caution.................................................................................. 9 Pin Configuration and Function Descriptions........................... 10 Definitions of Specifications ..................................................... 12 Typical Performance Characteristics ........................................... 13 Mode Control (via SPI Port)..................................................... 18 Register Description................................................................... 20 Functional Description.............................................................. 22 Serial Interface for Register Control ........................................ 22 General Operation of the Serial Interface ............................... 22 Instruction Byte .......................................................................... 23 R/W .............................................................................................. 23 N1, N0 .......................................................................................... 23 A4, A3, A2, A1, A0....................................................................... 23 Serial Interface Port Pin Descriptions ..................................... 23 MSB/LSB Transfers..................................................................... 23 Notes on Serial Port Operation ................................................ 25 DAC Operation........................................................................... 25 1R/2R Mode ................................................................................ 26 CLOCK Input Configuration ................................................... 26 Programmable PLL .................................................................... 27 Power Dissipation....................................................................... 29 Sleep/Power-Down Modes........................................................ 29 Two Port Data Input Mode ....................................................... 29 PLL Enabled, Two-Port Mode .................................................. 30 DATACLK Inversion.................................................................. 30 DATACLK Driver Strength....................................................... 30 PLL Enabled, One-Port Mode .................................................. 30 ONEPORTCLK Inversion......................................................... 31 ONEPORTCLK Driver Strength.............................................. 31 IQ Pairing .................................................................................... 31 PLL Disabled, Two-Port Mode ................................................. 31 PLL Disabled, One-Port Mode ................................................. 32 Digital Filter Modes ................................................................... 32 Amplitude Modulation.............................................................. 32 Modulation, No Interpolation .................................................. 34 Modulation, Interpolation = 2x ............................................... 35 Modulation, Intermodulation = 4x.......................................... 36 Modulation, Intermodulation = 8x.......................................... 37 Zero Stuffing ............................................................................... 38 Interpolating (Complex Mix Mode) ........................................ 38 Operations on Complex Signals............................................... 38 Complex Modulation and Image Rejection of Baseband Signals .......................................................................................... 39 Image Rejection and Sideband Suppressions of Modulated Carriers ........................................................................................ 41 Applying the AD9777 Output Configurations....................... 46 Unbuffered Differential Output, Equivalent Circuit ............. 46 Differential Coupling Using a Transformer............................ 46 Differential Coupling Using an Op Amp ................................ 47 Interfacing the AD9777 with the AD8345 Quadrature Modulator.................................................................................... 47 Evaluation Board ........................................................................ 48 Outline Dimensions ....................................................................... 58 Ordering Guide .......................................................................... 58
Rev. B | Page 2 of 60
AD9777
REVISION HISTORY
6/04--Data Sheet Changed from Rev. A to Rev. B. Changes to DC Specifications ....................................................... 5 Changes to Absolute Maximum Ratings...................................... 8 Changes to DAC Operation Section........................................... 25 Changes to Figure 49, Figure 50, and Figure 51 ........................ 29 Changes to the PLL Enabled, One-Port Mode Section ............ 30 Changes to the PLL Disabled, One-Port Mode Section ........... 32 Changes to the Ordering Guide .................................................. 57 Updated the Outline Dimensions ............................................... 57 3/03--Data Sheet Changed from Rev. 0 to Rev. A. Edits to Features .............................................................................. 1 Edits to DC Specifications ............................................................. 3 Edits to Dynamic Specifications.................................................... 4 Edits to Pin Function Descriptions............................................... 7 Edits to Table I ............................................................................... 14 Edits to Register Description--Address 02h Section ............... 15 Edits to Register Description--Address 03h Section ............... 16 Edits to Register Description--Address 07h, 0Bh Section ...... 16 Edits to Equation 1........................................................................ 16 Edits to MSB/LSB Transfers Section........................................... 18 Changes to Figure 8 ...................................................................... 20 Edits to Programmable PLL Section........................................... 21 Added new Figure 14.................................................................... 22 Renumbered Figures 15 to 69...................................................... 22 Added Two-Port Data Input Mode Section .............................. 23 Edits to PLL Enabled, Two-Port Mode Section......................... 24 Edits to Figure 19 ......................................................................... 24 Edits to Figure 21 .......................................................................... 25 Edits to PLL Disabled, Two-Port Mode Section ....................... 25 Edits to Figure 22 .......................................................................... 25 Edits to Figure 23 .......................................................................... 26 Edits to Figure 26a ........................................................................ 27 Changes to Figures 53 and 54...................................................... 38 Edits to Evaluation Board Section .............................................. 39 Changes to Figures 56 to 59......................................................... 40 Replaced Figures 60 to 69 ............................................................ 42 Updated Outline Dimensions...................................................... 49 7/02--Revision 0: Initial Version
Rev. B | Page 3 of 60
AD9777 GENERAL DESCRIPTION
(continued from Page 1) The selectable 2x/4x/8x interpolation filters simplify the requirements of the reconstruction filters while simultaneously enhancing the TxDAC+ family's pass-band noise/distortion performance. The independent channel gain and offset adjust registers allow the user to calibrate LO feedthrough and sideband suppression errors associated with analog quadrature modulators. The 6 dB of gain adjustment range can also be used to control the output power level of each DAC. The AD9777 features the ability to perform fS/2, fS/4, and fS/8 digital modulation and image rejection when combined with an analog quadrature modulator. In this mode, the AD9777 accepts I and Q complex data (representing a single or multicarrier waveform), generates a quadrature modulated IF signal along with its orthogonal representation via its dual DACs, and presents these two reconstructed orthogonal IF carriers to an analog quadrature modulator to complete the image rejection upconversion process. Another digital modulation mode (i.e., the direct IF mode) allows the original baseband signal representation to be frequency translated such that pairs of images fall at multiples of one-half the DAC update rate. The AD977x family includes a flexible clock interface accepting differential or single-ended sine wave or digital logic inputs. An internal PLL clock multiplier is included and generates the necessary on-chip high frequency clocks. It can also be disabled to allow the use of a higher performance external clock source. An internal programmable divider simplifies clock generation in the converter when using an external clock source. A flexible data input interface allows for straight binary or twos complement formats and supports single-port interleaved or dual-port data. Dual high performance DAC outputs provide a differential current output programmable over a 2 mA to 20 mA range. The AD9777 is manufactured on an advanced 0.35 micron CMOS process, operates from a single supply of 3.1 V to 3.5 V, and consumes 1.2 W of power. Targeted at wide dynamic range, multicarrier, and multistandard systems, the superb baseband performance of the AD9777 is ideal for wideband CDMA, multicarrier CDMA, multicarrier TDMA, multicarrier GSM, and high performance systems employing high-order QAM modulation schemes. The image rejection feature simplifies and can help to reduce the number of signal band filters needed in a transmit signal chain. The direct IF mode helps to eliminate a costly mixer stage for a variety of communications systems.
PRODUCTS HIGHLIGHTS
1. The AD9777 is the 16-bit member of the AD977x pin compatible, high performance, programmable 2x/4x/8x interpolating TxDAC+ family. Direct IF transmission is possible for 70 MHz + IFs through a novel digital mixing process. fS/2, fS/4, and fS/8 digital quadrature modulation and user selectable image rejection simplify/remove cascaded SAW filter stages. A 2x/4x/8x user selectable interpolating filter eases data rate and output signal reconstruction filter requirements. User selectable twos complement/straight binary data coding. User programmable channel gain control over 1 dB range in 0.01 dB increments. User programmable channel offset control 10% over the FSR. Ultrahigh speed 400 MSPS DAC conversion rate. Internal clock divider provides data rate clock for easy interfacing.
2. 3.
4. 5. 6. 7. 8. 9.
10. Flexible clock input with single-ended or differential input, CMOS, or 1 V p-p LO sine wave input capability. 11. Low power: Complete CMOS DAC operates on 1.2 W from a 3.1 V to 3.5 V single supply. The 20 mA full-scale current can be reduced for lower power operation, and several sleep functions are provided to reduce power during idle periods. 12. On-chip voltage reference: The AD9777 includes a 1.20 V temperature compensated band gap voltage reference. 13. An 80-lead thermally enhanced TQFP.
Rev. B | Page 4 of 60
AD9777 SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted. Table 1. DC Specifications
Parameter RESOLUTION DC Accuracy1 Integral Nonlinearity Differential Nonlinearity ANALOG OUTPUT (for 1R and 2R Gain Setting Modes) Offset Error Gain Error (with Internal Reference) Gain Matching Full-Scale Output Current2 Output Compliance Range Output Resistance Output Capacitance Gain, Offset Cal DACs, Monotonicity Guaranteed REFERENCE OUTPUT Reference Voltage Reference Output Current3 REFERENCE INPUT Input Compliance Range Reference Input Resistance Small Signal Bandwidth TEMPERATURE COEFFICIENTS Offset Drift Gain Drift (with Internal Reference) Reference Voltage Drift POWER SUPPLY AVDD Voltage Range Analog Supply Current (IAVDD)4 IAVDD in SLEEP Mode CLKVDD (PLL OFF) Voltage Range Clock Supply Current (ICLKVDD)4 CLKVDD (PLL ON) Clock Supply Current (ICLKVDD) DVDD Voltage Range Digital Supply Current (IDVDD)4 Nominal Power Dissipation4 PDIS5 PDIS in PWDN Power Supply Rejection Ratio--AVDD OPERATING RANGE Min 16 Typ Max Unit Bits LSB LSB % of FSR % of FSR % of FSR mA V k pF
-6.5 -0.025 -1.0 -1 2 -1.0
6 3 0.01 0.1
+6.5 +0.025 +1.0 +1 20 +1.25
200 3
1.14
1.20 100
1.26
V nA V k MHz ppm of FSR/C ppm of FSR/C ppm/C
0.1 7 0.5 0 50 50
1.25
3.1
3.3 72.5 23.3 3.3 8.5 23.5
3.5 76 26 3.5 10.0
V mA mA V mA mA
3.1
3.1
3.3 34 380 1.75 6.0 0.4
3.5 41 410
-40
+85
V mA mW W mW % of FSR/V C
1 2
Measured at IOUTA driving a virtual ground. Nominal full-scale current, IOUTFS, is 32x the IREF current. 3 Use an external amplifier to drive any external load. 4 100 MSPS fDAC with fOUT = 1 MHz, all supplies = 3.3 V, no interpolation, no modulation. 5 400 MSPS fDAC, fDATA = 50 MSPS, fS/2 modulation, PLL enabled.
Rev. B | Page 5 of 60
AD9777
TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 0 V, IOUTFS = 20 mA, Interpolation = 2x, differential transformer-coupled output, 50 doubly terminated, unless otherwise noted. Table 2. Dynamic Specifications
Parameter DYNAMIC PERFORMANCE Maximum DAC Output Update Rate (fDAC) Output Settling Time (tST) (to 0.025%) Output Rise Time (10% to 90%)1 Output Fall Time (10% to 90%)1 Output Noise (IOUTFS = 20 mA) AC LINEARITY--BASEBAND MODE Spurious-Free Dynamic Range (SFDR) to Nyquist (fOUT = 0 dBFS) fDATA = 100 MSPS, fOUT = 1 MHz fDATA = 65 MSPS, fOUT = 1 MHz fDATA = 65 MSPS, fOUT = 15 MHz fDATA = 78 MSPS, f fOUT = 1 MHz fDATA = 78 MSPS, fOUT = 15 MHz fDATA = 160 MSPS, fOUT = 1 MHz fDATA = 160 MSPS, fOUT = 15 MHz Spurious-Free Dynamic Range within a 1 MHz Window fOUT = 0 dBFS, fDATA = 100 MSPS, fOUT = 1 MHz Two-Tone Intermodulation (IMD) to Nyquist (fOUT1 = fOUT2 = -6 dBFS) fDATA = 65 MSPS, fOUT1 = 10 MHz; fOUT2 = 11 MHz fDATA = 65 MSPS, fOUT1 = 20 MHz; fOUT2 = 21 MHz fDATA = 78 MSPS, fOUT1 = 10 MHz; fOUT2 = 11 MHz fDATA = 78 MSPS, fOUT1 = 20 MHz; fOUT2 = 21 MHz fDATA = 160 MSPS, fOUT1 = 10 MHz; fOUT2 = 11 MHz fDATA = 160 MSPS, fOUT1 = 20 MHz; fOUT2 = 21 MHz Total Harmonic Distortion (THD) fDATA = 100 MSPS, fOUT = 1 MHz; 0 dBFS Signal-to-Noise Ratio (SNR) fDATA = 78 MSPS, fOUT = 5 MHz; 0 dBFS fDATA = 160 MSPS, fOUT = 5 MHz; 0 dBFS Adjacent Channel Power Ratio (ACPR) WCDMA with 3.84 MHz BW, 5 MHz Channel Spacing IF = Baseband, fDATA = 76.8 MSPS IF = 19.2 MHz, fDATA = 76.8 MSPS Four-Tone Intermodulation 21 MHz, 22 MHz, 23 MHz, and 24 MHz at -12 dBFS (fDATA = MSPS, Missing Center) AC LINEARITY--IF MODE Four-Tone Intermodulation at IF = 200 MHz 201 MHz, 202 MHz, 203 MHz, and 204 MHz at -12 dBFS (fDATA = 160 MSPS, fDAC = 320 MHz) Min 400 11 0.8 0.8 50 Typ Max Unit MSPS ns ns ns pA/Hz
71
85 85 84 85 83 85 83 99.1 85 78 85 78 85 84
dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dB dB dB
73
-71
-83 79 75
73 73 76
dBc dBc dBFS
72
dBFS
1
Measured single-ended into 50 load.
Rev. B | Page 6 of 60
AD9777
TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted. Table 3. Digital Specifications
Parameter DIGITAL INPUTS Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Input Capacitance CLOCK INPUTS Input Voltage Range Common-Mode Voltage Differential Voltage SERIAL CONTROL BUS Maximum SCLK Frequency (fSLCK) Mimimum Clock Pulse Width High (tPWH) Mimimum Clock Pulse Width Low (tPWL) Maximum Clock Rise/Fall Time Minimum Data/Chip Select Setup Time (tDS) Minimum Data Hold Time (tDH) Maximum Data Valid Time (tDV) RESET Pulse Width Inputs (SDI, SDIO, SCLK, CSB) Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Input Capacitance SDIO Output Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Min 2.1 -10 -10 5 0 0.75 0.5 15 30 30 1 25 0 30 1.5 2.1 -10 -10 5 DRVDD - 0.6 0.4 30 30 50 50 3 0 3 2.25 Typ 3 0 Max Unit V V A A pF V V V MHz ns ns ms ns ns ns ns V V A A pF V V mA mA
0.9 +10 +10
1.5 1.5
0.9 +10 +10
Rev. B | Page 7 of 60
AD9777
Digital Filter Specifications Table 4. Half-Band Filter No. 1 (43 Coefficients)
Tap 1, 43 2, 42 3, 41 4, 40 5, 39 6, 38 7, 37 8, 36 9, 35 10, 34 11, 33 12, 32 13, 31 14, 30 15, 29 16, 28 17, 27 18, 26 19, 25 20, 24 21, 23 22 Coefficient 8 0 -29 0 67 0 -134 0 244 0 -414 0 673 0 -1,079 0 1,772 0 -3,280 0 10,364 16,384
20 0
ATTENUATION (dBFS)
-20
-40
-60 -80
-100
0
0.5
1.0
1.5
2.0
fOUT (NORMALIZED TO INPUT DATA RATE)
Figure 2. 2x Interpolating Filter Response
20
0 -20
ATTENUATION (dBFS)
-40
-60
-80 -100
Table 5. Half-Band Filter No. 2 (19 Coefficients)
Tap 1, 19 2, 18 3, 17 4, 16 5, 15 6, 14 7, 13 8, 12 9, 11 10 Coefficient 19 0 -120 0 438 0 -1,288 0 5,047 8,192
02706-B-004
02706-B-005
-120 0 0.5 1.0 1.5 2.0
fOUT (NORMALIZED TO INPUT DATA RATE)
Figure 3. 4x Interpolating Filter Response
20
0 -20
ATTENUATION (dBFS)
-40
Table 6. Half-Band Filter No. 3 (11 Coefficients)
Tap 1, 11 2, 10 3, 9 4, 8 5, 7 6 Coefficient 7 0 -53 0 302 512
-60
-80
-100 -120 0 2 4 6 8
fOUT (NORMALIZED TO INPUT DATA RATE)
Figure 4. 8x Interpolating Filter Response
Rev. B | Page 8 of 60
02706-B-003
-120
AD9777 ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter AVDD, DVDD, CLKVDD AVDD, DVDD, CLKVDD AGND, DGND, CLKGND REFIO, FSADJ1/FSADJ2 IOUTA, IOUTB P1B15 to P1B0, P2B15 to P2B0 DATACLK/PLL_LOCK CLK+, CLK-, RESET LPF SPI_CSB, SPI_CLK, SPI_SDIO, SPI_SDO Junction Temperature Storage Temperature Lead Temperature (10 sec) With Respect To AGND, DGND, CLKGND AVDD, DVDD, CLKVDD AGND, DGND, CLKGND AGND AGND DGND DGND CLKGND CLKGND DGND Min -0.3 -4.0 -0.3 -0.3 -1.0 -0.3 -0.3 -0.3 -0.3 -0.3 -65 Max +4.0 +4.0 +0.3 AVDD + 0.3 AVDD + 0.3 DVDD + 0.3 DVDD + 0.3 CLKVDD + 0.3 CLKVDD + 0.3 DVDD + 0.3 125 +150 300 Unit V V V V V V V V V V C C C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
THERMAL CHARACTERISTICS
Thermal Resistance 80-Lead Thermally Enhanced TQFP JA = 23.5C/W (With thermal pad soldered to PCB)
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. B | Page 9 of 60
AD9777 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
IOUTA1 IOUTB1 AGND IOUTA2 IOUTB2 AGND AGND AVDD AGND AVDD AGND AGND AGND AGND AVDD AGND AVDD AGND AVDD AVDD
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
CLKVDD 1 LPF 2 CLKVDD 3 CLKGND 4 CLK+ CLK- CLKGND DATACLK/PLL_LOCK
5 6 7 8
PIN 1 IDENTIFIER
60 59 58 57 56 55 54
FSADJ1 FSADJ2 REFIO RESET SPI_CSB SPI_CLK SPI_SDIO SPI_SDO DGND DVDD P2B0 (LSB) P2B1 P2B2 P2B3 P2B4 P2B5 DGND DVDD P2B6 P2B7
DGND 9 DVDD 10 P1B15 (MSB) 11 P1B14 12 P1B13 13 P1B12 14 P1B11 15 P1B10 16 DGND 17 DVDD 18 P1B9 19 P1B8 20
AD9777
TxDAC+ TOP VIEW (Not to Scale)
53 52 51 50 49 48 47 46 45 44 43 42 41
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
IQSEL/P2B15 (MSB) ONEPORTCLK/P2B14
P1B7
P1B6
P1B5
P1B4 DGND
P1B3 P1B2
P1B1
P2B10 P2B9
P2B13 P2B12
P1B0 (LSB)
P2B11
DVDD
DGND DVDD
P2B8
Figure 5. Pin Configuration
Rev. B | Page 10 of 60
02706-B-002
AD9777
Table 8. Pin Function Description
Pin No. 1, 3 2 4, 7 5 6 8 Mnemonic CLKVDD LPF CLKGND CLK+ CLK- DATACLK/PLL_LOCK Description Clock Supply Voltage. PLL Loop Filter. Clock Supply Common. Differential Clock Input. Differential Clock Input. With the PLL enabled, this pin indicates the state of the PLL. A read of a Logic 1 indicates the PLL is in the locked state. Logic 0 indicates the PLL has not achieved lock. This pin may also be programmed to act as either an input or output (Address 02h, Bit 3) DATACLK signal running at the input data rate. Digital Common. Digital Supply Voltage. Port 1 Data Inputs.
9, 17, 25, 35, 44, 52 10, 18, 26, 36, 43, 51 11 to 16, 19 to 24, 27 to 30 31
DGND DVDD P1B15 (MSB) to P1B0 (LSB)
IQSEL/P2B15 (MSB)
32
ONEPORTCLK/P2B14
33, 34, 37 to 42, 45 to 50 53
P2B13 to P2B0 (LSB) SPI_SDO
In one-port mode, IQSEL = 1 followed by a rising edge of the differential input clock will latch the data into the I channel input register. IQSEL = 0 will latch the data into the Q channel input register. In two-port mode, this pin becomes the Port 2 MSB. With the PLL disabled and the AD9777 in one-port mode, this pin becomes a clock output that runs at twice the input data rate of the I and Q channels. This allows the AD9777 to accept and demux interleaved I and Q data to the I and Q input registers. Port 2 Data Inputs. In the case where SDIO is an input, SDO acts as an output. When SDIO becomes an output, SDO enters a High-Z state. This pin can also be used as an output for the data rate clock. For more information, see the Two Port Data Input Mode section. Bidirectional Data Pin. Data direction is controlled by Bit 7 of Register Address 00h. The default setting for this bit is 0, which sets SDIO as an input. Data input to the SPI port is registered on the rising edge of SPI_CLK. Data output on the SPI port is registered on the falling edge. Chip Select/SPI Data Synchronization. On momentary logic high, resets SPI port logic and initializes instruction cycle. Logic 1 resets all of the SPI port registers, including Address 00h, to their default values. A software reset can also be done by writing a Logic 1 to SPI Register 00h, Bit 5. However, the software reset has no effect on the bits in Address 00h. Reference Output, 1.2 V Nominal. Full-Scale Current Adjust, Q Channel. Full-Scale Current Adjust, I Channel. Analog Supply Voltage. Analog Common.
54 55 56 57
SPI_SDIO SPI_CLK SPI_CSB RESET
58 59 60 61, 63, 65, 76, 78, 80 62, 64, 66, 67, 70, 71, 74, 75, 77, 79 68, 69 72, 73
REFIO FSADJ2 FSADJ1 AVDD AGND
IOUTB2, IOUTA2 IOUTB1, IOUTA1
Differential DAC Current Outputs, Q Channel. Differential DAC Current Outputs, I Channel.
Rev. B | Page 11 of 60
AD9777
DEFINITIONS OF SPECIFICATIONS
Adjacent Channel Power Ratio (ACPR) A ratio in dBc between the measured power within a channel relative to its adjacent channel. Complex Image Rejection In a traditional two-part upconversion, two images are created around the second IF frequency. These images are redundant and have the effect of wasting transmitter power and system bandwidth. By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected. Complex Modulation The process of passing the real and imaginary components of a signal through a complex modulator (transfer function = ejt = cost + jsint) and realizing real and imaginary components on the modulator output. Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Gain Error The difference between the actual and ideal output span. The actual span is determined by the output when all inputs are set to 1 minus the output when all inputs are set to 0. Glitch Impulse Asymmetrical switching times in a DAC give rise to undesired output transients that are quantified by a glitch impulse. It is specified as the net area of the glitch in pV-s. Group Delay Number of input clocks between an impulse applied at the device input and the peak DAC output current. A half-band FIR filter has constant group delay over its entire frequency range. Impulse Response Response of the device to an impulse applied to the input. Interpolation Filter If the digital inputs to the DAC are sampled at a multiple rate of fDATA (interpolation rate), a digital filter can be constructed that has a sharp transition band near fDATA/2. Images that would typically appear around fDAC (output data rate) can be greatly suppressed. Linearity Error (Also Called Integral Nonlinearity or INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Monotonicity A DAC is monotonic if the output either increases or remains constant as the digital input increases. Offset Error The deviation of the output current from the ideal of 0 is called offset error. For IOUTA, 0 mA output is expected when the inputs are all 0. For IOUTB, 0 mA output is expected when all inputs are set to 1. Output Compliance Range The range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance. Pass Band Frequency band in which any input applied therein passes unattenuated to the DAC output. Power Supply Rejection The maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels. Spurious-Free Dynamic Range The difference, in dB, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. Settling Time The time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition. Stop-Band Rejection The amount of attenuation of a frequency outside the pass band applied to the DAC, relative to a full-scale signal applied at the DAC input within the pass band. Temperature Drift It is specified as the maximum change from the ambient (25C) value to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per C. For reference drift, the drift is reported in ppm per C. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured fundamental. It is expressed as a percentage or in decibels (dB).
Rev. B | Page 12 of 60
AD9777 TYPICAL PERFORMANCE CHARACTERISTICS
T = 25C, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, IOUTFS = 20 mA, Interpolation = 2x, differential transformer-coupled output, 50 doubly terminated, unless otherwise noted.
10 0 -10 10 0 -10
AMPLITUDE (dBm)
AMPLITUDE (dBm)
-20 -30 -40 -50 -60 -70 -80
02706-B-006
-20 -30 -40 -50 -60 -70 -80
02706-B-009
-90 0 65 FREQUENCY (MHz) 130
-90 0 50 100 FREQUENCY (MHz) 150
Figure 6. Single-Tone Spectrum @ fDATA = 65 MSPS with fOUT = fDATA/3
90 0dBFS 85 -6dBFS 80 75 70 -12dBFS 65 60 55
02706-B-007
Figure 9. Single-Tone Spectrum @ fDATA = 78 MSPS with fOUT = fDATA/3
90 85 80 75 70 -12dBFS 65 60 55
02706-B-010 02706-B-011
0dBFS
SFDR (dBc)
SFDR (dBc)
-6dBFS
50 0 5 10 15 20 25 30 FREQUENCY (MHz)
50 0 5 10 15 20 25 30 FREQUENCY (MHz)
Figure 7. In-Band SFDR vs. fOUT @ fDATA = 65 MSPS
90 85 -12dBFS 80 75 70 -6dBFS 65 60 55
02706-B-008
Figure 10. In-Band SFDR vs. fOUT @ fDATA = 78 MSPS
90 0dBFS 85
0dBFS 80 75 70 -6dBFS 65 60 55 50 0 5
-12dBFS
SFDR (dBc)
50 0 5 10 15 20 25 30 FREQUENCY (MHz)
SFDR (dBc)
10
15
20
25
30
FREQUENCY (MHz)
Figure 8. Out-of-Band SFDR vs. fOUT @ fDATA = 65 MSPS
Figure 11. Out-of-Band SFDR vs. fOUT @ fDATA = 78 MSPS
Rev. B | Page 13 of 60
AD9777
10 0 -10
80
AMPLITUDE (dBm)
90 0dBFS 85
-20 -30 -40 -50 -60
60
IMD (dBc)
75 70 65
-3dBFS -6dBFS
-70 -80
02706-B-012
55
02706-B-015 02706-B-017 02706-B-016
-90 0 100 200 FREQUENCY (MHz) 300
50 0 5 10 15 20 25 30 FREQUENCY (MHz)
Figure 12. Single-Tone Spectrum @ fDATA = 160 MSPS with fOUT = fDATA/3
90 0dBFS 85 80 75 70 65 60 55
02706-B-013
Figure 15. Third-Order IMD Products vs. Two-Tone fOUT @ fDATA = 65 MSPS
90 0dBFS 85 80 75 -3dBFS 70 65 60 55 50 0 5 10 15 20 25 30 FREQUENCY (MHz) -6dBFS
SFDR (dBc)
-6dBFS
-12dBFS
50 0 10 20 30 40 50 FREQUENCY (MHz)
Figure 13. In-Band SFDR vs. fOUT @ fDATA = 160 MSPS
90 85 80 75 -6dBFS 70 65 60 55
02706-B-014
IMD (dBc)
Figure 16. Third-Order IMD Products vs. Two-Tone fOUT @ fDATA = 78 MSPS
90 0dBFS 85 80 -3dBFS 75 -6dBFS 70 65
SFDR (dBc)
-12dBFS
0dBFS
IMD (dBc)
60 55 50 0 10 20 30 40 50 60 FREQUENCY (MHz)
50 0 10 20 30 40 50 FREQUENCY (MHz)
Figure 14. Out-of-Band SFDR vs. fOUT @ fDATA = 160 MSPS
Figure 17. Third-Order IMD Products vs. Two-Tone fOUT @ fDATA = 160 MSPS
Rev. B | Page 14 of 60
AD9777
90 85 80 75 70 65 60 55
02706-B-018
4x
90 0dBFS 85 -3dBFS 80
8x 1x 2x
-6dBFS
IMD (dBc)
IMD (dBc)
75 70 65 60 55
02706-B-021 02706-B-023 02706-B-022
50 0 10 20 30 40 50 60 FREQUENCY (MHz)
50 3.1
3.2
3.3 AVDD (V)
3.4
3.5
Figure 18. Third-Order IMD Products vs. Two-Tone fOUT and Interpolation Rate, 1x fDATA = 160 MSPS, 2x fDATA = 160 MSPS, 4x fDATA = 80 MSPS, 8x fDATA = 50 MSPS
90 85 80 4x 75 70 65 60 55
02706-B-019
Figure 21. Third-Order IMD Products vs. AVDD @ fOUT = 10 MHz, fDAC = 320 MSPS, fDATA = 160 MSPS
90 85 PLL OFF 80 75 70 PLL ON 65 60 55 50 0 50 100 150 INPUT DATA RATE (MSPS)
8x
IMD (dBc)
1x 2x
50 -15
-10 AOUT (dBFS)
-5
0
SNR (dB)
Figure 19. Third-Order IMD Products vs. Two-Tone AOUT and Interpolation Rate, fDATA = 50 MSPS in All Cases, 1x fDAC = 50 MSPS, 2x fDAC = 100 MSPS, 4x fDAC = 200 MSPS, 8x fDAC = 400 MSPS
90 85 80 -6dBFS 75 70 65 60 55
02706-B-020
Figure 22. SNR vs. Data Rate for fOUT = 5 MHz
90 78MSPS
0dBFS
85 80 75 70 65 60 55 50 -50
SFDR (dBc)
SFDR (dBc)
fDATA = 65MSPS
160MSPS
-12dBFS
50 3.1
3.2
3.3 AVDD (V)
3.4
3.5
0
50
100
TEMPERATURE (C)
Figure 20. SFDR vs. AVDD fOUT = 10 MHz, fDAC = 320 MSPS, fDATA = 160 MSPS
Figure 23. SFDR vs. Temperature @ fOUT = fDATA/11
Rev. B | Page 15 of 60
AD9777
0 -10 -20 AMPLITUDE (dBm)
AMPLITUDE (dBm)
-20 0
-30 -40 -50 -60 -70 -80 -90
02706-B-024
-40
-60
-80
0
50
100
150
0
5
10
15
20
25
30
35
40
45
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 24. Single-Tone Spurious Performance, fOUT = 10 MHz, fDATA = 150 MSPS, No Interpolation
0
Figure 27. Two-Tone IMD Performance, fDATA = 90 MSPS, Interpolation = 4x
0 -10
-20
-20
AMPLITUDE (dBm)
AMPLITUDE (dBm)
-30 -40 -50 -60 -70 -80 -90
-40
-60
-80
02706-B-025
0
10
20
30
40
50
0
50
100
150
200
250
300
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 25. Two-Tone IMD Performance, fDATA = 150 MSPS, No Interpolation
0 -10 -20 -20 0
Figure 28. Single-Tone Spurious Performance, fOUT = 10 MHz, fDATA = 80 MSPS, Interpolation = 4x
AMPLITUDE (dBm)
-40 -50 -60 -70 -80 -90
02706-B-026
AMPLITUDE (dBm)
-30
-40
-60
-80
0
50
100
150
200
250
300
0
5
10
15
20
25
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 26. Single-Tone Spurious Performance, fOUT = 10 MHz, fDATA = 150 MSPS, Interpolation = 2x
Figure 29. Two-Tone IMD Performance, fOUT = 10 MHz, fDATA = 50 MSPS, Interpolation = 8x
Rev. B | Page 16 of 60
02706-B-029
-100
-100
02706-B-028
-100
-100
02706-B-027
-100
-100
AD9777
0 -10 -20 AMPLITUDE (dBm)
AMPLITUDE (dBm)
0 -10 -20 -30 -40 -50 -60 -70 -80 -90
02706-B-031
-30 -40 -50 -60 -70 -80 -90
02706-B-030
-100 0 100 200 FREQUENCY (MHz) 300 400
-100 0 20 40 FREQUENCY (MHz) 60 80
Figure 30. Single-Tone Spurious Performance, fOUT = 10 MHz, fDATA = 50 MSPS, Interpolation = 8x
Figure 31. Eight-Tone IMD Performance, fDATA = 160 MSPS, Interpolation = 8x
Rev. B | Page 17 of 60
AD9777
MODE CONTROL (VIA SPI PORT)
Table 9. Mode Control via SPI Port (Default Values Are Highlighted)
Address 00h Bit 7 SDIO Bidirectional 0 = Input 1 = I/O Bit 6 LSB, MSB First 0 = MSB 1 = LSB Bit 5 Software Reset on Logic 1 Bit 4 Sleep Mode Logic 1 shuts down the DAC output currents Modulation Mode (None, fS/2, fS/4, fS/8) Bit 3 Power-Down Mode Logic 1 shuts down all digital and analog functions. 0 = No Zero Stuffing on Interpolation Filters, Logic 1 enables zero stuffing Bit 2 1R/2R Mode DAC output current set by one or two external resistors 0 = 2R, 1 = 1R 1 = Real Mix Mode 0 = Complex Mix Mode Bit 1 PLL_LOCK Indicator Bit 0
01h
Filter Interpolation Rate (1x, 2x, 4x, 8x)
Filter Interpolation Rate (1x, 2x, 4x, 8x)
Modulation Mode (None, fS/2, fS/4, fS/8)
0 = e-jt 1 = e+jt
02h
0 = Signed Input Data 1= Unsigned Data Rate1 Clock Output 0 = PLL OFF1 1 = PLL ON
0 = Two-Port Mode 1 = One-Port Mode
DATACLK Driver Strength
DATACLK Invert 0 = No Invert 1 = Invert
ONEPORTCLK Invert 0 = No Invert 1 = Invert
03h
04h
05h
IDAC Fine Gain Adjustment
0 = Automatic Charge Pump Control 1= Programmable IDAC Fine Gain Adjustment
PLL Charge Pump Control IDAC Fine Gain Adjustment IDAC Fine Gain Adjustment IDAC Fine Gain Adjustment IDAC Coarse Gain Adjustment IDAC Offset Adjustment Bit 5 IDAC Fine Gain Adjustment IDAC Coarse Gain Adjustment IDAC Offset Adjustment Bit 4
IQSEL Invert 0 = No Invert 1 = Invert PLL Divide (Prescaler) Ratio PLL Charge Pump Control IDAC Fine Gain Adjustment IDAC Coarse Gain Adjustment IDAC Offset Adjustment Bit 3 IDAC Offset Adjustment Bit 1
DATACLK/ PLL_LOCK1 Select 0= PLL_LOCK 1= DATACLK Q First 0 = I First 1 = Q First
PLL Divide (Prescaler) Ratio PLL Charge Pump Control IDAC Fine Gain Adjustment IDAC Coarse Gain Adjustment IDAC Offset Adjustment Bit 2 IDAC Offset Adjustment Bit 0
06h
07h
IDAC Offset IDAC Offset Adjustment Adjustment Bit 9 Bit 8 08h IDAC IOFFSET Direction 0 = IOFFSET on IOUTA 1 = IOFFSET on IOUTB 09h QDAC QDAC Fine Gain Fine Gain Adjustment Adjustment Table 9 continued on next page.
IDAC Offset Adjustment Bit 7
IDAC Offset Adjustment Bit 6
QDAC Fine Gain Adjustment
QDAC Fine Gain Adjustment
QDAC Fine Gain Adjustment
QDAC Fine Gain Adjustment
QDAC Fine Gain Adjustment
QDAC Fine Gain Adjustment
Rev. B | Page 18 of 60
AD9777
Address 0Ah Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 QDAC Coarse Gain Adjustment QDAC Offset Adjustment Bit 5 Bit 2 QDAC Coarse Gain Adjustment QDAC Offset Adjustment Bit 4 Bit 1 QDAC Coarse Gain Adjustment QDAC Offset Adjustment Bit 3 QDAC Offset Adjustment Bit 1 Bit 0 QDAC Coarse Gain Adjustment QDAC Offset Adjustment Bit 2 QDAC Offset Adjustment Bit 0
0Bh
QDAC Offset Adjustment Bit 9 QDAC IOFFSET Direction 0 = IOFFSET on IOUTA 1 = IOFFSET on IOUTB
QDAC Offset Adjustment Bit 8
QDAC Offset Adjustment Bit 7
QDAC Offset Adjustment Bit 6
0Ch
0Dh
Version Register
Version Register
Version Register
Version Register
1
For more information, see the Two Port Data Input Mode section.
Rev. B | Page 19 of 60
AD9777
REGISTER DESCRIPTION
Address 00h Bit 7: Logic 0 (default) causes the SPI_SDIO pin to act as an input during the data transfer (Phase 2) of the communications cycle. When set to 1, SPI_SDIO can act as an input or output, depending on Bit 7 of the instruction byte. Bit 6: Logic 0 (default). Determines the direction (LSB/MSB first) of the communications and data transfer communications cycles. Refer to the MSB/LSB Transfers section for more details. Bit 5: Writing a 1 to this bit resets the registers to their default values and restarts the chip. The RESET bit always reads back 0. Register Address 00h bits are not cleared by this software reset. However, a high level at the RESET pin forces all registers, including those in Address 00h, to their default state. Bit 4: Sleep Mode. A Logic 1 to this bit shuts down the DAC output currents. Bit 3: Power-Down. Logic 1 shuts down all analog and digital functions except for the SPI port. Bit 2: 1R/2R Mode. The default (0) places the AD9777 in two resistor mode. In this mode, the IREF currents for the I and Q DAC references are set separately by the RSET resistors on FSADJ2 and FSADJ1 (Pins 59 and 60). In 2R mode, assuming the coarse gain setting is full scale and the fine gain setting is 0, IFULLSCALE1 = 32 x VREF/FSADJ1 and IFULLSCALE2 = 32 x VREF/FSADJ2. With this bit set to 1, the reference currents for both I and Q DACs are controlled by a single resistor on Pin 60. IFULLSCALE in one resistor mode for both the I and Q DACs is half of what it would be in 2R mode, assuming all other conditions (RSET, register settings) remain unchanged. The full-scale current of each DAC can still be set to 20 mA by choosing a resistor of half the value of the RSET value used in 2R mode. Bit 1: PLL_LOCK Indicator. When the PLL is enabled, reading this bit will give the status of the PLL. A Logic 1 indicates the PLL is locked. A Logic 0 indicates an unlocked state. Address 01h Bits 7, 6: This is the filter interpolation rate according to the following table. 00 1x 01 2x 10 4x 11 8x Bits 5, 4: This is the modulation mode according to the following table. 00 none 01 fS/2 10 fS/4 11 fS/8 Bit 3: Logic 1 enables zero stuffing mode for interpolation filters. Bit 2: Default (1) enables the real mix mode. The I and Q data channels are individually modulated by fS/2, fS/4, or fS/8 after the interpolation filters. However, no complex modulation is done. In the complex mix mode (Logic 0), the digital modulators on the I and Q data channels are coupled to create a digital complex modulator. When the AD9777 is applied in conjunction with an external quadrature modulator, rejection can be achieved of either the higher or lower frequency image around the second IF frequency (i.e., the LO of the analog quadrature modulator external to the AD9777) according to the bit value of Register 01h, Bit 1. Bit 1: Logic 0 (default) causes the complex modulation to be of the form e-jt, resulting in the rejection of the higher frequency image when the AD9777 is used with an external quadrature modulator. A Logic 1 causes the modulation to be of the form e+jt, which causes rejection of the lower frequency image. Bit 0: In two-port mode, a Logic 0 (default) causes Pin 8 to act as a lock indicator for the internal PLL. A Logic 1 in this register causes Pin 8 to act as a DATACLK. For more information, see the Two Port Data Input Mode section. Address 02h Bit 7: Logic 0 (default) causes data to be accepted on the inputs as twos complement binary. Logic 1 causes data to be accepted as straight binary. Bit 6: Logic 0 (default) places the AD9777 in two-port mode. I and Q data enters the AD9777 via Ports 1 and 2, respectively. A Logic 1 places the AD9777 in one-port mode in which interleaved I and Q data is applied to Port 1. See Table 8 for detailed information on how to use the DATACLK/PLL_LOCK, IQSEL, and ONEPORTCLK modes. Bit 5: DATACLK Driver Strength. With the internal PLL disabled and this bit set to Logic 0, it is recommended that DATACLK be buffered. When this bit is set to Logic 1, DATACLK acts as a stronger driver capable of driving small capacitive loads. Bit 4: Default Logic 0. A value of 1 inverts DATACLK at Pin 8. Bit 2: Default Logic 0. A value of 1 inverts ONEPORTCLK at Pin 32. Bit 1: The default of Logic 0 causes IQSEL = 0 to direct input data to the I channel, while IQSEL = 1 directs input data to the Q channel. Bit 0: The default of Logic 0 defines IQ pairing as IQ, IQ, ..., while programming a Logic 1 causes the pair ordering to be QI, QI,...
Rev. B | Page 20 of 60
AD9777
Address 03h Bit 7: This allows the data rate clock (divided down from the DAC clock) to be output at either the DATACLK/PLL_LOCK pin (Pin 8) or at the SPI_SDO pin (Pin 53). The default of 0 in this register will enable the data rate clock at DATACLK/PLL_LOCK, while a 1 in this register will cause the data rate clock to be output at SPI_SDO. For more information, see the Two Port Data Input Mode section. Bits 1, 0: Setting this divide ratio to a higher number allows the VCO in the PLL to run at a high rate (for best performance) while the DAC input and output clocks run substantially slower. The divider ratio is set according to the following table. 00 01 10 11 Address 04h Bit 7: Logic 0 (default) disables the internal PLL. Logic 1 enables the PLL. Bit 6: Logic 0 (default) sets the charge pump control to automatic. In this mode, the charge pump bias current is controlled by the divider ratio defined in Address 03h, Bits 1 and 0. Logic 1 allows the user to manually define the charge pump bias current using Address 04h, Bits 2, 1, and 0. Adjusting the charge pump bias current allows the user to optimize the noise/settling performance of the PLL. Bits 2, 1, 0: With the charge pump control set to manual, these bits define the charge pump bias current according to the following table. 000 001 010 011 111 50 A 100 A 200 A 400 A 800 A /1 /2 /4 /8 Address 05h, 09h Bits 7 to 0: These bits represent an 8-bit binary number (Bit 7 MSB) that defines the fine gain adjustment of the I (05h) and Q (09h) DAC according to Equation 1. Address 06h, 0Ah Bits 3 to 0: These bits represent a 4-bit binary number (Bit 3 MSB) that defines the coarse gain adjustment of the I (06h) and Q (0Ah) DACs according to Equation 1. Address 07h, 0Bh Bits 7 to 0: These bits are used in conjunction with Address 08h, 0Ch, Bits 1, 0. Address 08h, 0Ch Bits 1, 0: The 10 bits from these two address pairs (07h, 08h and 0Bh, 0Ch) represent a 10-bit binary number that defines the offset adjustment of the I and Q DACs according to Equation 1. (07h, 0Bh-Bit 7 MSB/08h, 0Ch-Bit 0 LSB). Address 08h, 0Ch Bit 7: This bit determines the direction of the offset of the I (08h) and Q (0Ch) DACs. A Logic 0 will apply a positive offset current to IOUTA, while a Logic 1 will apply a positive offset current to IOUTB. The magnitude of the offset current is defined by the bits in Addresses 07h, 0Bh, 08h, 0Ch according to Equation 1. Equation 1 shows IOUTA and IOUTB as a function of fine gain, coarse gain, and offset adjustment when using 2R mode. In 1R mode, the current IREF is created by a single FSADJ resistor (Pin 60). This current is divided equally into each channel so that a scaling factor of one-half must be added to these equations for full-scale currents for both DACs and the offset.
6 x I REF I OUTA = 8
COARSE + 1 3 x I REF FINE 1024 DATA - x 16 ( A) 16 32 256 24 2
6 x I REF COARSE + 1 3 x I REF FINE 1024 216 - DATA - 1 ( A) I OUTB = - x 16 216 32 256 24 8 OFFSET I OFFSET = 4 x I REF ( A) 1024
(1)
Rev. B | Page 21 of 60
AD9777
FUNCTIONAL DESCRIPTION
The AD9777 dual interpolating DAC consists of two data channels that can be operated completely independently or coupled to form a complex modulator in an image reject transmit architecture. Each channel includes three FIR filters, making the AD9777 capable of 2x, 4x or 8x interpolation. High speed input and output data rates can be achieved within the following limitations.
Interpolation Rate (MSPS) 1x 2x 4x 8x Input Data Rate (MSPS) 160 160 100 50 DAC Sample Rate (MSPS) 160 320 400 400
SDO (PIN 53) SDIO (PIN 54) SCLK (PIN 55) CSB (PIN 56) AD9777 SPI PORT INTERFACE
02706-B-032
Figure 32. SPI Port Interface
SERIAL INTERFACE FOR REGISTER CONTROL
The AD9777 serial port is a flexible, synchronous serial communications port that allows easy interface to many industry-standard microcontrollers and microprocessors. The serial I/O is compatible with most synchronous transfer formats, including both the Motorola SPI and Intel SSR protocols. The interface allows read/write access to all registers that configure the AD9777. Single- or multiple-byte transfers are supported as well as MSB first or LSB first transfer formats. The AD9777's serial interface port can be configured as a single pin I/O (SDIO) or two unidirectional pins for I/O (SDIO/SDO).
Both data channels contain a digital modulator capable of mixing the data stream with an LO of fDAC/2, fDAC/4, or fDAC/8, where fDAC is the output data rate of the DAC. A zero stuffing feature is also included and can be used to improve pass-band flatness for signals being attenuated by the SIN(x)/x characteristic of the DAC output. The speed of the AD9777, combined with its digital modulation capability, enables direct IF conversion architectures at 70 MHz and higher. The digital modulators on the AD9777 can be coupled to form a complex modulator. By using this feature with an external analog quadrature modulator, such as the Analog Devices AD8345, an image rejection architecture can be enabled. To optimize the image rejection capability, as well as LO feedthrough in this architecture, the AD9777 offers programable (via the SPI port) gain and offset adjust for each DAC. Also included on the AD9777 are a phase-locked loop (PLL) clock multiplier and a 1.20 V band gap voltage reference. With the PLL enabled, a clock applied to the CLK+/CLK- inputs is frequency multiplied internally and generates all necessary internal synchronization clocks. Each 16-bit DAC provides two complementary current outputs whose full-scale currents can be determined either from a single external resistor or independently from two separate resistors (see the 1R/2R Mode section). The AD9777 features a low jitter, differential clock input that provides excellent noise rejection while accepting a sine or square wave input. Separate voltage supply inputs are provided for each functional block to ensure optimum noise and distortion performance. Sleep and power-down modes can be used to turn off the DAC output current (sleep) or the entire digital and analog sections (power-down) of the chip. An SPI compliant serial port is used to program the many features of the AD9777. Note that in power-down mode, the SPI port is the only section of the chip still active.
GENERAL OPERATION OF THE SERIAL INTERFACE
There are two phases to a communication cycle with the AD9777. Phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9777 coincident with the first eight SCLK rising edges. The instruction byte provides the AD9777 serial port controller with information regarding the data transfer cycle, which is Phase 2 of the communication cycle. The Phase 1 instruction byte defines whether the upcoming data transfer is read or write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer. The first eight SCLK rising edges of each communication cycle are used to write the instruction byte into the AD9777. A Logic 1 on the SPI_CSB pin, followed by a logic low, will reset the SPI port timing to the initial state of the instruction cycle. This is true regardless of the present state of the internal registers or the other signal levels present at the inputs to the SPI port. If the SPI port is in the middle of an instruction cycle or a data transfer cycle, none of the present data will be written. The remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the AD9777 and the system controller. Phase 2 of the communication cycle is a transfer of one to four data bytes, as determined by the instruction byte. Normally, using one multibyte transfer is the preferred method. However, single byte data transfers are useful to reduce CPU overhead when register access requires one byte only. Registers change immediately upon writing to the last bit of each transfer byte.
Rev. B | Page 22 of 60
AD9777
INSTRUCTION BYTE
The instruction byte contains the information shown below.
N1 0 0 1 1 N0 0 1 0 1 Description Transfer 1 Byte Transfer 2 Bytes Transfer 3 Bytes Transfer 4 Bytes
SPI_CSB (Pin 56)--Chip Select Active low input starts and gates a communication cycle. It allows more than one device to be used on the same serial communications lines. The SPI_SDO and SPI_SDIO pins will go to a high impedance state when this input is high. Chip select should stay low during the entire communication cycle. SPI_SDIO (Pin 54)--Serial Data I/O Data is always written into the AD9777 on this pin. However, this pin can be used as a bidirectional data line. The configuration of this pin is controlled by Bit 7 of Register Address 00h. The default is Logic 0, which configures the SPI_SDIO pin as unidirectional. SPI_SDO (Pin 53)--Serial Data Out Data is read from this pin for protocols that use separate lines for transmitting and receiving data. In the case where the AD9777 operates in a single bidirectional I/O mode, this pin does not output data and is set to a high impedance state.
R/W
Bit 7 of the instruction byte determines whether a read or a write data transfer will occur after the instruction byte write. Logic 1 indicates read operation. Logic 0 indicates a write operation.
N1, N0
Bits 6 and 5 of the instruction byte determine the number of bytes to be transferred during the data transfer cycle. The bit decodes are shown in the following table.
MSB I7 R/W I6 N1 I5 N0 I4 A4 I3 A3 I2 A2 I1 A1 LSB I0 A0
MSB/LSB TRANSFERS
The AD9777 serial port can support both most significant bit (MSB) first or least significant bit (LSB) first data formats. This functionality is controlled by the LSB first bit in Register 0. The default is MSB first. When this bit is set active high, the AD9777 serial port is in LSB first format. In LSB first mode, the instruction byte and data bytes must be written from LSB to MSB. In LSB first mode, the serial port internal byte address generator increments for each byte of the multibyte communication cycle. When this bit is set default low, the AD9777 serial port is in MSB first format. In MSB first mode, the instruction byte and data bytes must be written from MSB to LSB. In MSB first mode, the serial port internal byte address generator decrements for each byte of the multibyte communication cycle. When incrementing from 1Fh, the address generator changes to 00h. When decrementing from 00h, the address generator changes to 1Fh.
A4, A3, A2, A1, A0
Bits 4, 3, 2, 1, and 0 of the instruction byte determine which register is accessed during the data transfer portion of the communications cycle. For multibyte transfers, this address is the starting byte address. The remaining register addresses are generated by the AD9777.
SERIAL INTERFACE PORT PIN DESCRIPTIONS
SPI_CLK (Pin 55)--Serial Clock The serial clock pin is used to synchronize data to and from the AD9777 and to run the internal state machines. SPI_CLK maximum frequency is 15 MHz. All data input to the AD9777 is registered on the rising edge of SPI_CLK. All data is driven out of the AD9777 on the falling edge of SCLK.
Rev. B | Page 23 of 60
AD9777
INSTRUCTION CYCLE CS
DATA TRANSFER CYCLE
SCLK
SDIO
R/W
I6(N)
I5(N)
I4
I3
I2
I1
I0
D7N
D6N
D20
D10
D00
02706-B-033 02706-B-034
SDO
D7N
D6N
D20
D10
D00
Figure 33. Serial Register Interface Timing MSB First
INSTRUCTION CYCLE CS
DATA TRANSFER CYCLE
SCLK
SDIO
I0
I1
I2
I3
I4
I5(N)
I6(N)
R/W
D00
D10
D20
D6N
D7N
SDO
D00
D10
D20
D6N
D7N
Figure 34. Serial Register Interface Timing LSB First
tDS
CS
tSCLK
tPWH
tPWL
SCLK
tDS
tDH
02706-B-035
SDIO
INSTRUCTION BIT 7
T INSTRUCTION BIT 6
Figure 35. Timing Diagram for Register Write to AD9777
CS
SCLK
tDV
SDIO DATA BIT N SDO DATA BIT N-1
02706-B-036
Figure 36. Timing Diagram for Register Read from AD9777
Rev. B | Page 24 of 60
AD9777
NOTES ON SERIAL PORT OPERATION
The AD9777 serial port configuration bits reside in Bits 6 and 7 of Register Address 00h. It is important to note that the configuration changes immediately upon writing to the last bit of the register. For multibyte transfers, writing to this register may occur during the middle of the communication cycle. Care must be taken to compensate for this new configuration for the remaining bytes of the current communication cycle. The same considerations apply to setting the reset bit in Register Address 00h. All other registers are set to their default values, but the software reset doesn't affect the bits in Register Address 00h. It is recommended to use only single byte transfers when changing serial port configurations or initiating a software reset. A write to Bits 1, 2, and 3 of Address 00h with the same logic levels as for Bits 7, 6, and 5 (bit pattern: XY1001YX binary) allows the user to reprogram a lost serial port configuration and to reset the registers to their default values. A second write to Address 00h with reset bit low and serial port configuration as specified above (XY) reprograms the OSC IN multiplier setting. A changed fSYSCLK frequency is stable after a maximum of 200 fMCLK cycles (equals wake-up time).
GAIN CONTROL REGISTERS
The offset control defines a small current that can be added to IOUTA or IOUTB (not both) on the IDAC and QDAC. The selection of which IOUT this offset current is directed toward is programmable via Register 08h, Bit 7 (IDAC) and Register 0Ch, Bit 7 (QDAC). Figure 42 shows the scale of the offset current that can be added to one of the complementary outputs on the IDAC and QDAC. Offset control can be used for suppression of LO leakage resulting from modulation of dc signal components. If the AD9777 is dc-coupled to an external modulator, this feature can be used to cancel the output offset on the AD9777 as well as the input offset on the modulator. Figure 42 shows a typical example of the effect that the offset control has on LO suppression.
FINE GAIN DAC FINE GAIN DAC OFFSET CONTROL OFFSET DAC REGISTERS
IDAC
IOUTA1 IOUTB1
1.2VREF REFIO 0.1F
COARSE GAIN DAC FSADJ1 FSADJ2 RSET1 RSET2
COARSE GAIN DAC
QDAC
IOUTA2 IOUTB2
DAC OPERATION
The dual 16-bit DAC output of the AD9777, along with the reference circuitry, gain, and offset registers, is shown in Figure 37 and Figure 38. Note that an external reference can be used by simply overdriving the internal reference with the external reference. Referring to the transfer functions in Equation 1, a reference current is set by the internal 1.2 V reference, the external RSET resistor, and the values in the coarse gain register. The fine gain DAC subtracts a small amount from this and the result is input to IDAC and QDAC, where it is scaled by an amount equal to 1024/24. Figure 39 and Figure 40 show the scaling effect of the coarse and fine adjust DACs. IDAC and QDAC are PMOS current source arrays, segmented in a 5-4-7 configuration. The five MSB control an array of 31 current sources. The next four bits consist of 15 current sources whose values are all equal to 1/16 of an MSB current source. The seven LSB are binary weighted fractions of the middle bits' current sources. All current sources are switched to either IOUTA or IOUTB, depending on the input code. The fine adjustment of the gain of each channel allows for improved balance of QAM modulated signals, resulting in improved modulation accuracy and image rejection. In the Interfacing the AD9777 with the AD8345 Quadrature Modulator section, the performance data shows to what degree image rejection can be improved when the AD9777 is used with an AD8345 quadrature modulator from Analog Devices, Inc.
AVDD
OFFSET OFFSET CONTROL DAC GAIN REGISTERS CONTROL REGISTERS
Figure 37. DAC Outputs, Reference Current Scaling, and Gain/Offset Adjust.
84A REFIO 7k
Figure 38. Internal Reference Equivalent Circuit
25
COARSE REFERENCE CURRENT (mA)
20
2R MODE 15
10 1R MODE 5
0 COARSE GAIN REGISTER CODE (ASSUMING RSET1, RSET2 = 1.9k)
02706-B-039
0
5
10
02706-B-038
0.7V
15
20
Figure 39. Coarse Gain Effect on IFULLSCALE
Rev. B | Page 25 of 60
02706-B-037
AD9777
0 0 -10 OFFSET REGISTER 1 ADJUSTED -0.5
FINE REFERENCE CURRENT (mA)
LO SUPPRESSION (dBFS)
1R MODE -1.0 2R MODE -1.5
-20 -30 -40 -50 -60 -70 OFFSET REGISTER 2 ADJUSTED, WITH OFFSET REGISTER 1 SET TO OPTIMIZED VALUE -768 -512 -256 0 256 512 768 1024
02706-B-042
-2.0
-2.5
-3.0
02706-B-040
0
200
400
600
800
1000
-80 -1024
FINE GAIN REGISTER CODE (ASSUMING RSET1, RSET2 = 1.9k)
DAC1, DAC2 (OFFSET REGISTER CODES)
Figure 42. Offset Adjust Control, Effect on LO Suppression Figure 40. Fine Gain Effect on IFULLSCALE
1R/2R MODE
In 2R mode, the reference current for each channel is set independently by the FSADJ resistor on that channel. The AD9777 can be programmed to derive its reference current from a single resistor on Pin 60 by putting the part into 1R mode. The transfer functions in Equation 1 are valid for 2R mode. In 1R mode, the current developed in the single FSADJ resistor is split equally between the two channels. The result is that in 1R mode, a scale factor of 1/2 must be applied to the formulas in Equation 1. The full-scale DAC current in 1R mode can still be set to as high as 20 mA by using the internal 1.2 V reference and a 950 resistor instead of the 1.9 k resistor typically used in 2R mode.
In Figure 42, the negative scale represents an offset added to IOUTB, while the positive scale represents an offset added to IOUTA of the respective DAC. Offset Register 1 corresponds to IDAC, while Offset Register 2 corresponds to QDAC. Figure 42 represents the AD9777 synthesizing a complex signal that is then dc-coupled to an AD8345 quadrature modulator with an LO of 800 MHz. The dc coupling allows the input offset of the AD8345 to be calibrated out as well. The LO suppression at the AD8345 output was optimized first by adjusting Offset Register 1 in the AD9777. When an optimal point was found (roughly Code 54), this code was held in Offset Register 1, and Offset Register 2 was adjusted. The resulting LO suppression is 70 dBFS. These are typical numbers, and the specific code for optimization will vary from part to part.
5
CLOCK INPUT CONFIGURATION
The clock inputs to the AD9777 can be driven differentially or single-ended. The internal clock circuitry has supply and ground (CLKVDD, CLKGND) separate from the other supplies on the chip to minimize jitter from internal noise sources. Figure 43 shows the AD9777 driven from a single-ended clock source. The CLK+/CLK- pins form a differential input (CLKIN) so that the statically terminated input must be dcbiased to the midswing voltage level of the clock driven input.
4
OFFSET CURRENT (mA)
3 2R MODE 2 1R MODE 1
AD9777
RSERIES CLK+
0 200 400 600 800 1000
02706-B-041
0 COARSE GAIN REGISTER CODE (ASSUMING RSET1, RSET2 = 1.9k)
CLKVDD VTHRESHOLD CLK- 0.1F CLKGND
02706-B-043
Figure 41. DAC Output Offset Current
Figure 43. Single-Ended Clock Driving Clock Inputs
Rev. B | Page 26 of 60
AD9777
A configuration for differentially driving the clock inputs is given in Figure 44. DC-blocking capacitors can be used to couple a clock driver output whose voltage swings exceed CLKVDD or CLKGND. If the driver voltage swings are within the supply range of the AD9777, the dc-blocking capacitors and bias resistors are not necessary.
AD9777
0.1F 1k CLK+ 1k ECL/PECL 0.1F 0.1F 1k CLK- 1k CLKGND
02706-B-044
PROGRAMMABLE PLL
CLKIN can function either as an input data rate clock (PLL enabled) or as a DAC data rate clock (PLL disabled) according to the state of Address 02h, Bit 7 in the SPI port register. The internal operation of the AD9777 clock circuitry in these two modes is illustrated in Figure 45 and Figure 46. The PLL clock multiplier and distribution circuitry produce the necessary internal synchronized 1x, 2x, 4x, and 8x clocks for the rising edge triggered latches, interpolation filters, modulators, and DACs. This circuitry consists of a phase detector, charge pump, voltage controlled oscillator (VCO), prescaler, clock distribution, and SPI port control. The charge pump,VCO, differential clock input buffer, phase detector, prescaler, and clock distribution are all powered from CLKVDD. PLL lock status is indicated by the logic signal at the PLL_LOCK pin, as well as by the status of Bit 1, Register 00h. To ensure optimum phase noise performance from the PLL clock multiplier and distribution, CLKVDD should originate from a clean analog supply. Table 10 defines the minimum input data rates versus the interpolation and PLL divider setting. If the input data rate drops below the defined minimum under these conditions, VCO phase noise may increase significantly. The VCO speed is a function of the input data rate, the interpolation rate, and the VCO prescaler, according to the following function:
CLKVDD
Figure 44. Differential Clock Driving Clock Inputs
A transformer, such as the T1-1T from Mini-Circuits, can also be used to convert a single-ended clock to differential. This method is used on the AD9777 evaluation board so that an external sine wave with no dc offset can be used as a differential clock. PECL/ECL drivers require varying termination networks, the details of which are left out of Figure 43 and Figure 44 but can be found in application notes such as AND8020/D from On Semiconductor. These networks depend on the assumed transmission line impedance and power supply voltage of the clock driver. Optimum performance of the AD9777 is achieved when the driver is placed very close to the AD9777 clock inputs, thereby negating any transmission line effects such as reflections due to mismatch. The quality of the clock and data input signals is important in achieving optimum performance. The external clock driver circuitry should provide the AD9777 with a low jitter clock input that meets the minimum/maximum logic levels while providing fast edges. Although fast clock edges help minimize any jitter that will manifest itself as phase noise on a reconstructed waveform, the high gain bandwidth product of the AD9777's clock input comparator can tolerate differential sine wave inputs as low as 0.5 V p-p, with minimal degradation of the output noise floor.
VCO Speed ( MHz ) = Input Data Rate ( MHz ) x Interpolation Rate x Prescaler
CLK+ PLL_LOCK 1 = LOCK 0 = NO LOCK CLK- PLLVDD
AD9777
INTERPOLATION FILTERS, MODULATORS, AND DACS 2 1 INPUT DATA LATCHES CLOCK DISTRIBUTION CIRCUITRY 4 8
PHASE DETECTOR
CHARGE PUMP
LPF
PRESCALER
VCO
SPI PORT
MODULATION RATE CONTROL
Figure 45. PLL and Clock Circuitry with PLL Enabled
Rev. B | Page 27 of 60
02706-B-045
INTERPOLATION RATE CONTROL
INTERNAL SPI CONTROL REGISTERS
PLL DIVIDER (PRESCALER) CONTROL PLL CONTROL (PLL ON)
AD9777
CLK+ PLL_LOCK 1 = LOCK 0 = NO LOCK CLK-
Table 11. Required PLL Prescaler Ration vs. fDATA
AD9777
INTERPOLATION FILTERS, MODULATORS, AND DACS 2 1 INPUT DATA LATCHES CLOCK DISTRIBUTION CIRCUITRY INTERNAL SPI CONTROL REGISTERS 4 8
PHASE DETECTOR
CHARGE PUMP
fDATA (MSPS) 125 125 100 75 50
0
PLL Disabled Enabled Enabled Enabled Enabled
Prescaler Ratio div 1 div 2 div 2 div 4
PRESCALER
VCO
-10 -20
PHASE NOISE (dBFS)
PLL DIVIDER (PRESCALER) CONTROL MODULATION RATE CONTROL
02706-B-046
-30 -40 -50 -60 -70 -80 -90 -100 0 1 2 3 4 5
02706-B-047
02706-B-048
INTERPOLATION RATE CONTROL
PLL CONTROL (PLL ON)
SPI PORT
Figure 46. PLL and Clock Circuitry with PLL Disabled
In addition, if the zero stuffing option is enabled, the VCO will double its speed again. Phase noise may be slightly higher with the PLL enabled. Figure 47 illustrates typical phase noise performance of the AD9777 with 2x interpolation and various input data rates. The signal synthesized for the phase noise measurement was a single carrier at a frequency of fDATA/4. The repetitive nature of this signal eliminates quantization noise and distortion spurs as a factor in the measurement. Although the curves blend together in Figure 47, the different conditions are given for clarity in the table above Figure 47. Figure 47 also contains a table detailing PLL divider settings versus interpolation rate and maximum and minimum fDATA rates. Note that maximum fDATA rates of 160 MSPS are due to the maximum input data rate of the AD9777. However, maximum rates of less than 160 MSPS and all minimum fDATA rates are due to maximum and minimum speeds of the internal PLL VCO. Figure 48 shows typical performance of the PLL lock signal (Pin 8 or 53) when the PLL is in the process of locking. Table 10. PLL Optimization
Interpolation Rate 1 1 1 1 2 2 2 2 4 4 4 4 8 8 8 8 Divider Setting 1 2 4 8 1 2 4 8 1 2 4 8 1 2 4 8 Minimum fDATA 32 16 8 4 24 12 6 3 24 12 6 3 24 12 6 3 Maximum fDATA 160 160 112 56 160 112 56 28 100 56 28 14 50 28 14 7
-110 FREQUENCY OFFSET (MHz)
Figure 47. Phase Noise Performance
Figure 48. PLL_LOCK Output Signal (Pin 8) in the Process of Locking (Typical Lock Time)
It is important to note that the resistor/capacitor needed for the PLL loop filter is internal on the AD9777. This will suffice unless the input data rate is below 10 MHz, in which case an external series RC is required between the and CLKVDD pins.
Rev. B | Page 28 of 60
AD9777
POWER DISSIPATION
The AD9777 has three voltage supplies: DVDD, AVDD, and CLKVDD. Figure 49, Figure 50, and Figure 51 show the current required from each of these supplies when each is set to the 3.3 V nominal specified for the AD9777. Power dissipation (PD) can easily be extracted by multiplying the given curves by 3.3. As Figure 49 shows, IDVDD is very dependent on the input data rate, the interpolation rate, and the activation of the internal digital modulator. IDVDD, however, is relatively insensitive to the modulation rate by itself. In Figure 50, IAVDD shows the same type of sensitivity to data, interpolation rate, and the modulator function but to a much lesser degree (<10%). In Figure 51, ICLKVDD varies over a wide range yet is responsible for only a small percentage of the overall AD9777 supply current requirement.
400 8x, (MOD. ON) 350 300 250 200 150 100 50
02706-B-049
35 8x 30 4x 25 2x
ICLKVDD (mA)
20
15 1x 10 5
0
50
100
150
200
fDATA (MHz)
Figure 51. ICLKVDD vs. fDATA vs. Interpolation Rate, PLL Disabled
2x, (MOD. ON) 4x, (MOD. ON)
SLEEP/POWER-DOWN MODES
(Control Register 00h, Bits 3 and 4) The AD9777 provides two methods for programmable reduction in power savings. The sleep mode, when activated, turns off the DAC output currents but the rest of the chip remains functioning. When coming out of sleep mode, the AD9777 will immediately return to full operation. Power-down mode, on the other hand, turns off all analog and digital circuitry in the AD9777 except for the SPI port. When returning from power-down mode, enough clock cycles must be allowed to flush the digital filters of random data acquired during the power-down cycle. Note that optimal performance with the PLL enabled is achieved with the UCO in the PLL control loop running at 450 MHz to 550 MHz.
8x
4x 2x
IDVDD (mA)
1x
0 0 50 100 150 200
fDATA (MHz)
Figure 49. IDVDD vs. fDATA vs. Interpolation Rate, PLL Disabled
TWO PORT DATA INPUT MODE
76.0 8x, (MOD. ON) 75.5 2x, (MOD. ON) 75.0 74.5 4x 74.0 73.5 73.0 1x 72.5
02706-B-050
4x, (MOD. ON)
8x
2x
The digital data input ports can be configured as two independent ports or as a single (one-port mode) port. In the two-port mode, data at the two input ports is latched into the AD9777 on every rising edge of the data rate clock (DATACLK). Also, in the two-port mode, the AD9777 can be programmed to generate an externally available DATACLK for the purpose of data synchronization. This data rate clock can be programmed to be available at either Pin 8 (DATACLK/PLL_LOCK) or Pin 53 (SPI_SDO). Because Pin 8 can also function as a PLL lock indicator when the PLL is enabled, there are several options for configuring Pins 8 and 53. The following describes these options.
200
IAVDD (mA)
72.0 0 50 100 150
PLL Off (Register 4, Bit 7 = 0) Register 3, Bit 7 = 0; DATACLK out of Pin 8. Register 3, Bit 7 = 1; DATACLK out of Pin 53. PLL On (Register 4, Bit 7 = 1) Register 3, Bit 7 = 0, Register 1, Bit 0 = 0; PLL lock indicator out of Pin 8.
fDATA (MHz)
Figure 50. IAVDD vs. fDATA vs. Interpolation Rate, PLL Disabled
Rev. B | Page 29 of 60
02706-B-051
0
AD9777
Register 3, Bit 7 = 1, Register 1, Bit 0 = 0; PLL lock indicator out of Pin 53. Register 3, Bit 7 = 0, Register 1, Bit 0 = 1; DATACLK out of Pin 8. Register 3, Bit 7 = 1, Register 1, Bit 0 = 1; DATACLK out of Pin 53. In one-port mode, P2B14 and P2B15 from input data port two are redefined as IQSEL and ONEPORTCLK, respectively. The input data in one-port mode is steered to one of the two internal data channels based on the logic level of IQSEL. A clock signal, ONEPORTCLK, is generated by the AD9777 in this mode for the purpose of data synchronization. ONEPORTCLK runs at the input interleaved data rate, which is 2x the data rate at the internal input to either channel. Test configurations showing the various clocks that are required and generated by the AD9777 with the PLL enabled/disabled and in the one-port/two-port modes are given in Figure 101 to Figure 104. Jumper positions needed to operate the AD9777 evaluation board in these modes are given as well.
tOD
CLKIN
DATACLK
DATA AT PORTS 1 AND 2
02706-B-052
tS
tH
tS = 0.0ns (MAX) tH = 2.5ns (MAX)
Figure 52. Timing Requirements in Two-Port Input Mode with PLL Enabled
DATACLK DRIVER STRENGTH
(Control Register 02h, Bit 5) The DATACLK output driver strength is capable of driving >10 mA into a 330 load while providing a rise time of 3 ns. Figure 53 shows DATACLK driving a 330 resistive load at a frequency of 50 MHz. By enabling the drive strength option (Control Register 02h, Bit 5), the amplitude of DATACLK under these conditions will be increased by approximately 200 mV.
3.0 2.5
PLL ENABLED, TWO-PORT MODE
(Control Register 02h, Bits 6 to 0 and 04h, Bits 7 to 1) With the phase-locked loop (PLL) enabled and the AD9777 in two-port mode, the speed of CLKIN is inherently that of the input data rate. In two-port mode, Pin 8 (DATACLK/PLL_ LOCK) can be programmed (Control Register 01h, Bit 0) to function as either a lock indicator for the internal PLL or as a clock running at the input data rate. When Pin 8 is used as a clock output (DATACLK), its frequency is equal to that of CLKIN. Data at the input ports is latched into the AD9777 on the rising edge of the CLKIN. Figure 52 shows the delay, tOD, inherent between the rising edge of CLKIN and the rising edge of DATACLK, as well as the setup and hold requirements for the data at Ports 1 and 2. The setup and hold times given in Figure 52 are the input data transitions with respect to CLKIN. Note that in two-port mode (PLL enabled or disabled), the data rate at the interpolation filter inputs is the same as the input data rate at Ports 1 and 2. The DAC output sample rate in two-port mode is equal to the clock input rate multiplied by the interpolation rate. If zero stuffing is used, another factor of 2 must be included to calculate the DAC sample rate.
2.0
AMPLITUDE (V)
1.5 1.0
0.5
0 DELTA APPROX. 2.8ns 0 10 20 TIME (ns) 30 40 50
02706-B-053
-0.5
Figure 53. DATACLK Driver Capability into 330 at 50 MHz
DATACLK INVERSION
(Control Register 02h, Bit 4) By programming this bit, the DATACLK signal shown in Figure 53 can be inverted. With inversion enabled, tOD will refer to the time between the rising edge of CLKIN and the falling edge of DATACLK. No other effect on timing will occur.
PLL ENABLED, ONE-PORT MODE
(Control Register 02h, Bits 6 to 1 and 04h, Bits 7 to 1) In one-port mode, the I and Q channels receive their data from an interleaved stream at digital input Port 1. The function of Pin 32 is defined as an output (ONEPORTCLK) that generates a clock at the interleaved data rate, which is 2x the internal input data rate of the I and Q channels. The frequency of CLKIN is equal to the internal input data rate of the I and Q channels. The selection of the data for the I or Q channel is determined by the state of the logic level at Pin 31 (IQSEL when the AD9777 is
Rev. B | Page 30 of 60
AD9777
in one-port mode) on the rising edge of ONEPORTCLK. Under these conditions, IQSEL = 0 will latch the data into the I channel on the clock rising edge, while IQSEL = 1 will latch the data into the Q channel. It is possible to invert the I and Q selection by setting Control Register 02h, Bit 1 to the invert state (Logic 1). Figure 54 illustrates the timing requirements for the data inputs as well as the IQSEL input. Note that the 1x interpolation rate is not available in one-port mode. The DAC output sample rate in one-port mode is equal to CLKIN multiplied by the interpolation rate. If zero stuffing is used, another factor of 2 must be included to calculate the DAC sample rate.
IQ PAIRING
(Control Register 02h, Bit 0) In one-port mode, the interleaved data is latched into the AD9777 internal I and Q channels in pairs. The order of how the pairs are latched internally is defined by this control register. The following is an example of the effect this has on incoming interleaved data. Given the following interleaved data stream, where the data indicates the value with respect to full scale.
I 0.5 Q 0.5 I 1 Q 1 I 0.5 Q 0.5 I 0 Q 0 I 0.5 Q 0.5
ONEPORTCLK INVERSION
(Control Register 02h, Bit 2) By programming this bit, the ONEPORTCLK signal shown in Figure 54 can be inverted. With inversion enabled, tOD refers to the delay between the rising edge of the external clock and the falling edge of ONEPORTCLK. The setup and hold times, tS and tH, will be with respect to the falling edge of ONEPORTCLK. There will be no other effect on timing.
With the control register set to 0 (I first), the data will appear at the internal channel inputs in the following order in time.
I Channel Q Channel 0.5 0.5 1 1 0.5 0.5 0 0 0.5 0.5
With the control register set to 1 (Q first), the data will appear at the internal channel inputs in the following order in time.
I Channel Q Channel 0.5 y 1 0.5 0.5 1 0 0.5 0.5 0 x 0.5
ONEPORTCLK DRIVER STRENGTH
The drive capability of ONEPORTCLK is identical to that of DATACLK in the two-port mode. Refer to Figure 53 for performance under load conditions.
tOD tOD = 4.0ns (MIN)
CLKIN TO 5.5ns (MAX)
The values x and y represent the next I value and the previous Q value in the series.
PLL DISABLED, TWO-PORT MODE
With the PLL disabled, a clock at the DAC output rate must be applied to CLKIN. Internal clock dividers in the AD9777 synthesize the DATACLK signal at Pin 8, which runs at the input data rate and can be used to synchronize the input data. Data is latched into input Ports 1 and 2 of the AD9777 on the rising edge of DATACLK. DATACLK speed is defined as the speed of CLKIN divided by the interpolation rate. With zero stuffing enabled, this division increases by a factor of 2. Figure 55 illustrates the delay between the rising edge of CLKIN and the rising edge of DATACLK, as well as tS and tH in this mode. The programmable modes DATACLK inversion and DATACLK driver strength described in the previous section (PLL Enabled, Two-Port Mode) have identical functionality with the PLL disabled.
tS = 3.0ns (MAX) tH = -0.5ns (MAX) tIQS = 3.5ns (MAX) tIQH = -1.5ns (MAX
ONEPORTCLK
I AND Q INTERLEAVED INPUT DATA AT PORT 1
tS tH
IQSEL
02706-B-054
tIQS
tIQH
Figure 54. Timing Requirements in One-Port Input Mode, with the PLL Enabled
The data rate CLK created by dividing down the DAC clock in this mode can be programmed (via Register x03h, Bit 7) to be output from the SPI_SDO pin, rather than the DATACLK pin. In some applications, this may improve complex image rejection. tOD will increase by 1.6 ns when SPI_SDO is used as data rate clock out.
Rev. B | Page 31 of 60
AD9777
tOD
tOD
CLKIN
CLKIN
DATACLK
ONEPORTCLK
DATA AT PORTS 1 AND 2
tS
tH
tOD = 6.5ns (MIN) TO 8.0ns (MAX) tS = 5.0ns (MAX) tH = -3.2ns (MAX)
Figure 55. Timing Requirements in Two-Port Input Mode, with PLL Disabled
02706-B-055
I AND Q INTERLEAVED INPUT DATA AT PORT 1
tS tH
PLL DISABLED, ONE-PORT MODE
IQSEL
In one-port mode, data is received into the AD9777 as an interleaved stream on Port 1. A clock signal (ONEPORTCLK), running at the interleaved data rate, which is 2x the input data rate of the internal I and Q channels, is available for data synchronization at Pin 32. With PLL disabled, a clock at the DAC output rate must be applied to CLKIN. Internal dividers synthesize the ONEPORTCLK signal at Pin 32. The selection of the data for the I or Q channel is determined by the state of the logic level applied to Pin 31 (IQSEL when the AD9777 is in one-port mode) on the rising edge of ONEPORTCLK. Under these conditions, IQSEL = 0 will latch the data into the I channel on the clock rising edge, while IQSEL = 1 will latch the data into the Q channel. It is possible to invert the I and Q selection by setting Control Register 02h, Bit 1 to the invert state (Logic 1). Figure 56 illustrates the timing requirements for the data inputs as well as the IQSEL input. Note that the 1x interpolation rate is not available in the one-port mode. One-port mode is very useful when interfacing with devices, such as the Analog Devices AD6622 or AD6623 transmit signal processors, in which two digital data channels have been interleaved (multiplexed). The programmable modes' ONEPORTCLK inversion, ONEPORTCLK driver strength, and IQ pairing described in the previous section (PLL Enabled, One-Port Mode) have identical functionality with the PLL disable.
tOD = 4.0ns (MIN)
Figure 56. Timing Requirements in One-Port Input Mode, with PLL Disabled
DIGITAL FILTER MODES
The I and Q data paths of the AD9777 have their own independent half-band FIR filters. Each data path consists of three FIR filters, providing up to 8x interpolation for each channel. The rate of interpolation is determined by the state of Control Register 01h, Bits 7 and 6. Figure 2 to Figure 4 show the response of the digital filters when the AD9777 is set to 2x, 4x, and 8x modes. The frequency axes of these graphs have been normalized to the input data rate of the DAC. As the graphs show, the digital filters can provide greater than 75 dB of out-ofband rejection. An online tool is available for quick and easy analysis of the AD9777 interpolation filters in the various modes. The link can be accessed at http://www.analog.com/Analog_Root/static/techsupport/design tools/interactiveTools/dac/ad9777image.html.
AMPLITUDE MODULATION
Given two sine waves at the same frequency but with a 90 phase difference, a point of view in time can be taken such that the waveform that leads in phase is cosinusoidal and the waveform that lags is sinusoidal. Analysis of complex variables states that the cosine waveform can be defined as having real positive and negative frequency components, while the sine waveform consists of imaginary positive and negative frequency images. This is shown graphically in the frequency domain in Figure 57.
Rev. B | Page 32 of 60
02706-B-056
TO 5.5ns (MAX) tOD = 4.7ns (MAX) tS = 3.0ns (MAX) tH = -1.0ns (MAX) tIQS = 3.5ns (MAX) tIQH = -1.5ns (MAX) (TYP SPECS)
tIQS
tIQH
AD9777
e-jt/2j SINE DC e-jt/2j
of the various modulation modes. The phase relationship of the modulated signals is dependent on whether the modulating carrier is sinusoidal or cosinusoidal, again with respect to the reference point of the viewer. Examples of sine and cosine modulation are given in Figure 58.
Ae-jt/2j
02706-B-057
e-jt/2
e-jt/2 COSINE DC
SINUSOIDAL MODULATION DC Ae-jt/2j Ae-jt/2 Ae-jt/2
02706-B-058
Figure 57. Real and Imaginary Components of Sinusoidal and Cosinusoidal Waveforms
Amplitude modulating a baseband signal with a sine or a cosine convolves the baseband signal with the modulating carrier in the frequency domain. Amplitude scaling of the modulated signal reduces the positive and negative frequency images by a factor of 2. This scaling will be very important in the discussion
COSINUSOIDAL MODULATION DC
Figure 58. Baseband Signal, Amplitude Modulated with Sine and Cosine Carriers
Rev. B | Page 33 of 60
AD9777
MODULATION, NO INTERPOLATION
With Control Register 01h, Bits 7 and 6 set to 00, the interpolation function on the AD9777 is disabled. Figure 59 to Figure 62 show the DAC output spectral characteristics of the AD9777 in the various modulation modes, all with the interpolation filters disabled. The modulation frequency is determined by the state of Control Register 01h, Bits 5 and 4. The tall rectangles represent the digital domain spectrum of a baseband signal of narrow bandwidth. By comparing the digital domain spectrum to the DAC SIN(x)/x roll-off, an estimate can be made for the characteristics required for the DAC reconstruction filter. Note also, per the previous discussion on amplitude modulation, that the spectral components (where modulation is set to fS/4 or fS/8) are scaled by a factor of 2. In the situation where the modulation is fS/2, the modulated spectral components add constructively, and there is no scaling effect.
The Effects of Digital Modulation on DAC Output Spectrum, Interpolation Disabled
0 0
-20
-20
AMPLITUDE (dBFS)
-40
AMPLITUDE (dBFS)
-40
-60
-60
-80
-80
02706-B-059
0
0.2
0.4
0.6
0.8
1.0
0
0.2
0.4
0.6
0.8
1.0
fOUT (xfDATA)
fOUT (xfDATA)
Figure 59. No Interpolation, Modulation Disabled
0 0
Figure 61. No Interpolation, Modulation = fDAC/4
-20
-20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
-40
-40
-60
-60
-80
-80
02706-B-060
0
0.2
0.4
0.6
0.8
1.0
0
0.2
0.4
0.6
0.8
1.0
fOUT (xfDATA)
fOUT (xfDATA)
Figure 60. No Interpolation, Modulation = fDAC/2
Figure 62. No Interpolation, Modulation = fDAC/8
Rev. B | Page 34 of 60
02706-B-062
-100
-100
02706-B-061
-100
-100
AD9777
MODULATION, INTERPOLATION = 2x
With Control Register 01h, Bits 7 and 6 set to 01, the interpolation rate of the AD9777 is 2x. Modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence (+1, -1). Figure 63 to Figure 66 represent the spectral response of the AD9777 DAC output with 2x interpolation in the various modulation modes to a narrow band baseband signal (again, the tall rectangles in the graphic). The advantage of interpolation becomes clear in Figure 63 to Figure 66, where it can be seen that the images that would normally appear in the spectrum around the significant point is that the interpolation filtering is done previous to the digital modulator. For this reason, as Figure 63 to Figure 66 show, the pass band of the interpolation filters can be frequency shifted, giving the equivalent of a high-pass digital filter. Note that when using the fS/4 modulation mode, there is no true stop band as the band edges coincide with each other. In the fS/8 modulation mode, amplitude scaling occurs over only a portion of the digital filter pass band due to constructive addition over just that section of the band
The Effects of Digital Modulation on DAC Output Spectrum, Interpolation = 2x
0 0
-20
-20
AMPLITUDE (dBFS)
-40
AMPLITUDE (dBFS)
02706-B-063
-40
-60
-60
-80
-80
0
0.5
1.0
1.5
2.0
0
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1.5
2.0
fOUT (xfDATA)
fOUT (xfDATA)
Figure 63. 2x Interpolation, Modulation = Disabled
0 0
Figure 65. 2x Interpolation, Modulation = fDAC/4
-20
-20
AMPLITUDE (dBFS)
-40
AMPLITUDE (dBFS)
-40
-60
-60
-80
-80
02706-B-064
0
0.5
1.0
1.5
2.0
0
0.5
1.0
1.5
2.0
fOUT (xfDATA)
fOUT (xfDATA)
Figure 64. 2x Interpolation, Modulation = fDAC/2
Figure 66. 2x Interpolation, Modulation = fDAC/8
Rev. B | Page 35 of 60
02706-B-066
-100
-100
02706-B-065
-100
-100
AD9777
MODULATION, INTERMODULATION = 4x
With Control Register 01h, Bits 7 and 6 set to 10, the interpolation rate of the AD9777 is 4x. Modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence (0, +1, 0, -1). Figure 67 to Figure 70 represent the spectral response of the AD9777 DAC output with 4x interpolation in the various modulation modes to a narrow band baseband signal.
The Effects of Digital Modulation on DAC Output Spectrum, Interpolation = 4x
0 0
-20
-20
AMPLITUDE (dBFS)
-40
AMPLITUDE (dBFS)
02706-B-067
-40
-60
-60
-80
-80
0
1
2
3
4
0
1
2
3
4
fOUT (xfDATA)
fOUT (xfDATA)
Figure 67. 4x Interpolation, Modulation Disabled
0 0
Figure 69. 4x Interpolation, Modulation = fDAC/4
-20
-20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
-40
-40
-60
-60
-80
-80
02706-B-068
0
1
2
3
4
0
1
2
3
4
fOUT (xfDATA)
fOUT (xfDATA)
Figure 68. 4x Interpolation, Modulation = fDAC/2
Figure 70. 4x Interpolation, Modulation = fDAC/8
Rev. B | Page 36 of 60
02706-B-070
-100
-100
02706-B-069
-100
-100
AD9777
MODULATION, INTERMODULATION = 8x
With Control Register 01h, Bits 7 and 6, set to 11, the interpolation rate of the AD9777 is 8x. Modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence (0, +0.707, +1, +0.707, 0, -0.707, -1, +0.707). Figure 71 to Figure 74 represent the spectral response of the AD9777 DAC output with 8x interpolation in the various modulation modes to a narrow band baseband signal. Looking at Figure 59 to Figure 75, the user can see how higher interpolation rates reduce the complexity of the reconstruction filter needed at the DAC output. It also becomes apparent that the ability to modulate by fS/2, fS/4, or fS/8 adds a degree of flexibility in frequency planning
The Effects of the Digital Modulation on the DAC Output Spectrum, Interpolation = 8x
0
0
-20
-20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
-40
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-80
02706-B-071
0
1
2
3
4
0
1
2
3
4
5
6
7
8
fOUT (xfDATA)
fOUT (xfDATA)
Figure 71. 8x Interpolation, Modulation Disabled
0
Figure 73. 8x Interpolation, Modulation = fDAC/4
0
-20
-20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
-40
-40
-60
-60
-80
-80
02706-B-072
0
1
2
3
4
0
1
2
3
4
5
6
7
8
fOUT (xfDATA)
fOUT (xfDATA)
Figure 72. 8x Interpolation, Modulation = fDAC/2
Figure 74. 8x Interpolation, Modulation = fDAC/8
Rev. B | Page 37 of 60
02706-B-074
-100
-100
02706-B-073
-100
-100
AD9777
ZERO STUFFING
(Control Register 01h, Bit 3) As shown in Figure 75, a 0 or null in the output frequency response of the DAC (after interpolation, modulation, and DAC reconstruction) occurs at the final DAC sample rate (fDAC). This is due to the inherent SIN(x)/x roll-off response in the digitalto-analog conversion. In applications where the desired frequency content is below fDAC/2, this may not be a problem. Note that at fDAC/2 the loss due to SIN(x)/x is 4 dB. In direct RF applications, this roll-off may be problematic due to the increased pass-band amplitude variation as well as the reduced amplitude of the desired signal. Consider an application where the digital data into the AD9777 represents a baseband signal around fDAC/4 with a pass band of fDAC/10. The reconstructed signal out of the AD9777 would experience only a 0.75 dB amplitude variation over its pass band. However, the image of the same signal occurring at 3x fDAC/4 will suffer from a pass-band flatness variation of 3.93 dB. This image may be the desired signal in an IF application using one of the various modulation modes in the AD9777. This rolloff of image frequencies can be seen in Figure 59 to Figure 74, where the effect of the interpolation and modulation rate is apparent as well.
10
The net effect is to increase the DAC output sample rate by a factor of 2x with the 0 in the SIN(x)/x DAC transfer function occurring at twice the original frequency. A 6 dB loss in amplitude at low frequencies is also evident, as can be seen in Figure 76. It is important to realize that the zero stuffing option by itself does not change the location of the images but rather their amplitude, pass-band flatness, and relative weighting. For instance, in the previous example, the pass-band amplitude flatness of the image at 3x fDATA/4 is now improved to 0.59 dB while the signal level has increased slightly from -10.5 dBFS to -8.1 dBFS.
INTERPOLATING (COMPLEX MIX MODE)
(Control Register 01h, Bit 2) In the complex mix mode, the two digital modulators on the AD9777 are coupled to provide a complex modulation function. In conjunction with an external quadrature modulator, this complex modulation can be used to realize a transmit image rejection architecture. The complex modulation function can be programmed for e+jt or e-jt to give upper or lower image rejection. As in the real modulation mode, the modulation frequency can be programmed via the SPI port for fDAC/2, fDAC/4, and fDAC/8, where fDAC represents the DAC output rate.
OPERATIONS ON COMPLEX SIGNALS
ZERO STUFFING ENABLED
0
SIN (X)/X ROLL-OFF (dBFS)
-10
-20
-30
ZERO STUFFING DISABLED
Truly complex signals cannot be realized outside of a computer simulation. However, two data channels, both consisting of real data, can be defined as the real and imaginary components of a complex signal. I (real) and Q (imaginary) data paths are often defined this way. By using the architecture defined in Figure 76, a system that operates on complex signals can be realized, giving a complex (real and imaginary) output. If a complex modulation function (e+jt) is desired, the real and imaginary components of the system correspond to the real and imaginary components of e+jt or cost and sint. As Figure 77 shows, the complex modulation function can be realized by applying these components to the structure of the complex system defined in Figure 76.
-40
0
0.5
1.0
1.5
2.0
fOUT, NORMALIZED TO fDATA WITH ZERO STUFFING DISABLED (Hz)
Figure 75. Effect of Zero Stuffing on DAC's SIN(x)/x Response
To improve upon the pass-band flatness of the desired image, the zero stuffing mode can be enabled by setting the control register bit to a Logic 1. This option increases the ratio of fDAC/fDATA by a factor of 2 by doubling the DAC sample rate and inserting a midscale sample (i.e., 1000 0000 0000 0000) after every data sample originating from the interpolation filter. This is important as it will affect the PLL divider ratio needed to keep the VCO within its optimum speed range. Note that the zero stuffing takes place in the digital signal chain at the output of the digital modulator, before the DAC.
02706-B-075
-50
a(t)
INPUT
OUTPUT
c(t) x b(t) + d x b(t)
COMPLEX FILTER = (c + jd) b(t) IMAGINARY INPUT OUTPUT b(t) x a(t) + c x b(t)
02706-B-076
Figure 76. Realization of a Complex System
Rev. B | Page 38 of 60
AD9777
INPUT (REAL) INPUT (IMAGINARY) OUTPUT (REAL)
INPUT (REAL) OUTPUT INPUT (IMAGINARY)
02706-B-078
90
SINt 90 COSt
Figure 78. Quadrature Modulation
02706-B-077
OUTPUT (IMAGINARY) e-jt = COSt + jSINt
Figure 77. Implementation of a Complex Modulator
COMPLEX MODULATION AND IMAGE REJECTION OF BASEBAND SIGNALS
In traditional transmit applications, a two-step upconversion is done in which a baseband signal is modulated by one carrier to an IF (intermediate frequency) and then modulated a second time to the transmit frequency. Although this approach has several benefits, a major drawback is that two images are created near the transmit frequency. Only one image is needed, the other being an exact duplicate. Unless the unwanted image is filtered, typically with analog components, transmit power is wasted and the usable bandwidth available in the system is reduced. A more efficient method of suppressing the unwanted image can be achieved by using a complex modulator followed by a quadrature modulator. Figure 78 is a block diagram of a quadrature modulator. Note that it is in fact the real output half of a complex modulator. The complete upconversion can actually be referred to as two complex upconversion stages, the real output of which becomes the transmitted signal.
The entire upconversion from baseband to transmit frequency is represented graphically in Figure 79. The resulting spectrum shown in Figure 79 represents the complex data consisting of the baseband real and imaginary channels, now modulated onto orthogonal (cosine and negative sine) carriers at the transmit frequency. It is important to remember that in this application (two baseband data channels), the image rejection is not dependent on the data at either of the AD9777 input channels. In fact, image rejection will still occur with either one or both of the AD9777 input channels active. Note that by changing the sign of the sinusoidal multiplying term in the complex modulator, the upper sideband image could have been suppressed while passing the lower one. This is easily done in the AD9777 by selecting the e+jt bit (Register 01h, Bit 1). In purely complex terms, Figure 79 represents the two-stage upconversion from complex baseband to carrier.
Rev. B | Page 39 of 60
AD9777
REAL CHANNEL (OUT) A/2 -FC1 REAL CHANNEL (IN) A DC -FC COMPLEX MODULATOR IMAGINARY CHANNEL (IN) -FC B DC B/2 B/2 -FC FC TO QUADRATURE MODULATOR A/2
FC
-B/2J
B/2J
IMAGINARY CHANNEL (OUT) -A/2J A/2J
-FC A/4 + B/4J A/4 - B/4J
FC A/4 + B/4J A/4 - B/4J
-FQ2 -FQ - FC -FQ + FC
FQ F Q - FC FQ + FC
OUT REAL -A/4 - B/4J A/4 - B/4J QUADRATURE MODULATOR IMAGINARY -FQ FQ A/4 + B/4J -A/4 + B/4J
REJECTED IMAGES A/2 + B/2J A/2 - B/2J
-FQ NOTES 1F = COMPLEX MODULATION FREQUENCY C 2F = QUADRATURE MODULATION FREQUENCY Q
FQ
02706-B-079
Figure 79. Two-Stage Upconversion and Resulting Image Rejection
Rev. B | Page 40 of 60
AD9777
COMPLEX BASEBAND SIGNAL 1 OUTPUT = REAL x ej(1 + 2)t
1/2 = REAL
1/2
02706-B-080
-1 - 2
DC
1 + 2 FREQUENCY
Figure 80. Two-Stage Complex Upconversion
IMAGE REJECTION AND SIDEBAND SUPPRESSIONS OF MODULATED CARRIERS
As shown in Figure 79, image rejection can be achieved by applying baseband data to the AD9777 and following the AD9777 with a quadrature modulator. To process multiple carriers while still maintaining image reject capability, each carrier must be complex modulated. As Figure 80 shows, single or multiple complex modulators can be used to synthesize complex carriers. These complex carriers are then summed and applied to the real and imaginary inputs of the AD9777. A system in which multiple baseband signals are complex
BASEBAND CHANNEL 1 REAL INPUT IMAGINARY INPUT R(1) COMPLEX MODULATOR 1 R(1)
modulated and then applied to the AD9777 real and imaginary inputs, followed by a quadrature modulator, is shown in Figure 82, which also describes the transfer function of this system and the spectral output. Note the similarity of the transfer functions given in Figure 82 and Figure 80.Figure 82 adds an additional complex modulator stage for the purpose of summing multiple carriers at the AD9777 inputs. Also, as in Figure 79, the image rejection is not dependent on the real or imaginary baseband data on any channel. Image rejection on a channel will occur if either the real or imaginary data, or both, is present on the baseband channel. It is important to remember that the magnitude of a complex signal can be 1.414x the magnitude of its real or imaginary components. Due to this 3 dB increase in signal amplitude, the real and imaginary inputs to the AD9777 must be kept at least 3 dB below full scale when operating with the complex modulator. Overranging in the complex modulator will result in severe distortion at the DAC output.
MULTICARRIER REAL OUTPUT = R(1) + R(2) + . . .R(N) (TO REAL INPUT OF AD9777)
BASEBAND CHANNEL 2 REAL INPUT IMAGINARY INPUT
R(2) COMPLEX MODULATOR 2 R(2) MULTICARRIER IMAGINARY OUTPUT = I(1) + I(2) + . . .I(N) (TO IMAGINARY INPUT OF AD9777) R(N) = REAL OUTPUT OF N I(N) = IMAGINARY OUTPUT OF N
IMAGINARY INPUT
R(N)
Figure 81. Synthesis of Multicarrier Complex Signal
MULTIPLE BASEBAND CHANNELS REAL MULTIPLE COMPLEX MODULATORS FREQUENCY = 1, 2...N REAL
AD9777
COMPLEX MODULATOR FREQUENCY = C
REAL QUADRATURE MODULATOR FREQUENCY = Q
02706-B-081
BASEBAND CHANNEL N REAL INPUT
R(N) COMPLEX MODULATOR N
REAL
IMAGINARY
IMAGINARY
IMAGINARY
COMPLEX BASEBAND SIGNAL x
ej(N + C + Q)t
OUTPUT = REAL
DC REJECTED IMAGES
Figure 82. Image Rejection with Multicarrier Signals
Rev. B | Page 41 of 60
02706-B-082
-1 - C - Q
1 + C + Q
AD9777
The complex carrier synthesized in the AD9777 digital modulator is accomplished by creating two real digital carriers in quadrature. Carriers in quadrature cannot be created with the modulator running at fDAC/2. As a result, complex modulation only functions with modulation rates of fDAC/4 and fDAC/8. Regions A and B of Figure 83 to Figure 88 are the result of the complex signal described previously, when complex modulated in the AD9777 by +ejt. Regions C and D are the result of the complex signal described previously, again with positive frequency components only, modulated in the AD9777 by -ejt. The analog quadrature modulator after the AD9777 inherently modulates by +ejt. Region A Region A is a direct result of the upconversion of the complex signal near baseband. If viewed as a complex signal, only the images in Region A will remain. The complex Signal A, consisting of positive frequency components only in the digital domain, has images in the positive odd Nyquist zones (1, 3, 5...), as well as images in the negative even Nyquist zones. The appearance and rejection of images in every other Nyquist zone will become more apparent at the output of the quadrature modulator. The A images will appear on the real and the imaginary outputs of the AD9777, as well as on the output of the quadrature modulator, where the center of the spectral plot will now represent the quadrature modulator LO and the horizontal scale now represents the frequency offset from this LO. Region B Region B is the image (complex conjugate) of Region A. If a spectrum analyzer is used to view the real or imaginary DAC outputs of the AD9777, Region B will appear in the spectrum. However, on the output of the quadrature modulator, Region B will be rejected. Region C Region C is most accurately described as a down conversion, as the modulating carrier is -ejt. If viewed as a complex signal, only the images in Region C will remain. This image will appear on the real and imaginary outputs of the AD9777, as well as on the output of the quadrature modulator, where the center of the spectral plot will now represent the quadrature modulator LO and the horizontal scale will represent the frequency offset from this LO. Region D Region D is the image (complex conjugate) of Region C. If a spectrum analyzer is used to view the real or imaginary DAC outputs of the AD9777, Region D will appear in the spectrum. However, on the output of the quadrature modulator, Region D will be rejected. Figure 89 to Figure 96 show the measured response of the AD9777 and AD8345 given the complex input signal to the AD9777 in Figure 89. The data in these graphs was taken with a data rate of 12.5 MSPS at the AD9777 inputs. The interpolation rate of 4x or 8x gives a DAC output data rate of 50 MSPS or 100 MSPS. As a result, the high end of the DAC output spectrum in these graphs is the first null point for the SIN(x)/x roll-off, and the asymmetry of the DAC output images is representative of the SIN(x)/x roll-off over the spectrum. The internal PLL was enabled for these results. In addition, a 35 MHz third-order low-pass filter was used at the AD9777/AD8345 interface to suppress DAC images. An important point can be made by looking at Figure 91 and Figure 93. Figure 91 represents a group of positive frequencies modulated by complex +fDAC/4, while Figure 93 represents a group of negative frequencies modulated by complex -fDAC/4. When looking at the real or imaginary outputs of the AD9777, as shown in Figure 91 and Figure 93, the results look identical. However, the spectrum analyzer cannot show the phase relationship of these signals. The difference in phase between the two signals becomes apparent when they are applied to the AD8345 quadrature modulator, with the results shown in Figure 92 and Figure 94.
Rev. B | Page 42 of 60
AD9777
0
0
-20 D -40 A B C D A B C
-20
-40 D A B CD A B C
-60
-60
-80
-80
02706-B-083
(LO) fOUT (xfDATA)
(LO) fOUT (xfDATA)
Figure 83. 2x Interpolation, Complex fDAC/4 Modulation
0 0
Figure 86. 2x Interpolation, Complex fDAC/8 Modulation
-20 D -40 A B C D A B C
-20
-40 DA B CD A B C
-60
-60
-80
-80
02706-B-084
(LO) fOUT (xfDATA)
(LO) fOUT (xfDATA)
Figure 84. 4x Interpolation, Complex fDAC/4 Modulation
0 0
Figure 87. 4x Interpolation, Complex fDAC/8 Modulation
-20 D -40 A B C D A B C
-20 DA -40 BC DA BC
-60
-60
-80
-80
02706-B-085
(LO) fOUT (xfDATA)
(LO) fOUT (xfDATA)
Figure 85. 8x Interpolation, Complex fDAC/4 Modulation
Figure 88. 8x Interpolation, Complex fDAC/8 Modulation
Rev. B | Page 43 of 60
02706-B-088
-100 -8.0
-6.0
-4.0
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0
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-100 -8.0
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02706-B-087
-100 -4.0
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-100 -4.0
-3.0
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02706-B-086
-100 -2.0
-1.5
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0
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-100 -2.0
-1.5
-1.0
-0.5
0
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AD9777
0 -10 -20 0 -10 -20
AMPLITUDE (dBm)
AMPLITUDE (dBm)
-30 -40 -50 -60 -70 -80 -90
02706-B-089
-30 -40 -50 -60 -70 -80 -90
02706-B-091 02706-B-092
-100 0 10 20 30 40 50 FREQUENCY (MHz)
-100 0 10 20 30 40 50 FREQUENCY (MHz)
Figure 89. AD9777, Real DAC Output of Complex Input Signal Near Baseband (Positive Frequencies Only), Interpolation = 4x, No Modulation in AD9777
0 -10 -20
Figure 91. AD9777, Real DAC Output of Complex Input Signal Near Baseband (Positive Frequencies Only), Interpolation = 4x, Complex Modulation in AD9777 = +fDAC/4
0 -10 -20
AMPLITUDE (dBm)
-40 -50 -60 -70 -80 -90
02706-B-090
AMPLITUDE (dBm)
760 770 780 790 800 810 820 830 840 850
-30
-30 -40 -50 -60 -70 -80 -90 -100 750
-100 750
760
770
780
790
800
810
820
830
840
850
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 90. AD9777 Complex Output from Figure 89, Now Quadrature Modulated by AD8345 (LO = 800 MHz)
Figure 92. AD9777 Complex Output from Figure 91, Now Quadrature Modulated by AD8345 (LO = 800 MHz)
Rev. B | Page 44 of 60
AD9777
0 -10 -20 -20 0
AMPLITUDE (dBm)
AMPLITUDE (dBm)
-30 -40 -50 -60 -70 -80 -90
02706-B-093
-40
-60
-80
0
10
20
30
40
50
0
20
40
60
80
100
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 93. AD9777, Real DAC Output of Complex Input Signal Near Baseband (Negative Frequencies Only), Interpolation = 4x, Complex Modulation in AD9777 = -fDAC/4
0 -10 -20
Figure 95. AD9777, Real DAC Output of Complex Input Signal Near Baseband (Positive Frequencies Only), Interpolation = 8x, Complex Modulation in AD9777 = +fDAC/8
0 -10 -20
AMPLITUDE (dBm)
AMPLITUDE (dBm)
-30 -40 -50 -60 -70 -80 -90
02706-B-094
-30 -40 -50 -60 -70 -80 -90
02706-B-096
-100 750
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-100 700
720
740
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800
820
840
860
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900
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 94. AD9777 Complex Output from Figure 93, Now Quadrature Modulated by AD8345 (LO = 800 MHz)
Figure 96. AD9777 Complex Output from Figure 95, Now Quadrature Modulated by AD8345 (LO = 800 MHz)
Rev. B | Page 45 of 60
02706-B-095
-100
-100
AD9777
APPLYING THE AD9777 OUTPUT CONFIGURATIONS
The following sections illustrate typical output configurations for the AD9777. Unless otherwise noted, it is assumed that IOUTFS is set to a nominal 20 mA. For applications requiring optimum dynamic performance, a differential output configuration is suggested. A simple differential output may be achieved by converting IOUTA and IOUTB to a voltage output by terminating them to AGND via equal value resistors. This type of configuration may be useful when driving a differential voltage input device such as a modulator. If a conversion to a singleended signal is desired and the application allows for ac coupling, an RF transformer may be useful; if power gain is required, an op amp may be used. The transformer configuration provides optimum high frequency noise and distortion performance. The differential op amp configuration is suitable for applications requiring dc coupling, signal gain, and/or level shifting within the bandwidth of the chosen op amp. A single-ended output is suitable for applications requiring a unipolar voltage output. A positive unipolar output voltage will result if IOUTA and/or IOUTB is connected to a load resistor, RLOAD, referred to AGND. This configuration is most suitable for a single-supply system requiring a dc-coupled, ground referred output voltage. Alternatively, an amplifier could be configured as an I-V converter, thus converting IOUTA or IOUTB into a negative unipolar voltage. This configuration provides the best DAC dc linearity as IOUTA or IOUTB are maintained at ground or virtual ground. For the typical situation, where IOUTFS = 20 mA and RA and RB both equal 50 , the equivalent circuit values become: VSOURCE = 2 VP-P ROUT = 100 Note that the output impedance of the AD9777 DAC itself is greater than 100 k and typically has no effect on the impedance of the equivalent output circuit.
DIFFERENTIAL COUPLING USING A TRANSFORMER
An RF transformer can be used to perform a differential-tosingle ended signal conversion, as shown in Figure 98. A differentially coupled transformer output provides the optimum distortion performance for output signals whose spectral content lies within the transformer's pass band. An RF transformer, such as the Mini-Circuits T1-1T, provides excellent rejection of common-mode distortion (i.e., even-order harmonics) and noise over a wide frequency range. It also provides electrical isolation and the ability to deliver twice the power to the load. Transformers with different impedance ratios may also be used for impedance matching purposes.
IOUTA DAC IOUTB MINI-CIRCUITS T1-1T
02706-B-098
RLOAD
Figure 98. Transformer-Coupled Output Circuit
UNBUFFERED DIFFERENTIAL OUTPUT, EQUIVALENT CIRCUIT
In many applications, it may be necessary to understand the equivalent DAC output circuit. This is especially useful when designing output filters or when driving inputs with finite input impedances. Figure 97 illustrates the output of the AD9777 and the equivalent circuit. A typical application where this information may be useful is when designing an interface filter between the AD9777 and the Analog Devices AD8345 quadrature modulator.
IOUTA IOUTB VOUT+ VOUT-
The center tap on the primary side of the transformer must be connected to AGND to provide the necessary dc current path for both IOUTA and IOUTB. The complementary voltages appearing at IOUTA and IOUTB (i.e., VOUTA and VOUTB) swing symmetrically around AGND and should be maintained within the specified output compliance range of the AD9777. A differential resistor, RDIFF, may be inserted in applications where the output of the transformer is connected to the load, RLOAD, via a passive reconstruction filter or cable. RDIFF is determined by the transformer's impedance ratio and provides the proper source termination that results in a low VSWR. Note that approxmately half the signal power will be dissipated across RDIFF.
RA + RB VSOURCE = IOUTFS x (RA + RB) p-p
Figure 97. DAC Output Equivalent Circuit
02706-B-097
VOUT (DIFFERENTIAL)
Rev. B | Page 46 of 60
AD9777
DIFFERENTIAL COUPLING USING AN OP AMP
An op amp can also be used to perform a differential-to-single ended conversion, as shown in Figure 99. This has the added benefit of providing signal gain as well. In Figure 99, the AD9777 is configured with two equal load resistors, RLOAD, of 25 . The differential voltage developed across IOUTA and IOUTB is converted to a single-ended signal via the differential op amp configuration. An optional capacitor can be installed across IOUTA and IOUTB, forming a real pole in a low-pass filter. The addition of this capacitor also enhances the op amp's distortion performance by preventing the DAC's fast slewing output from overloading the input of the op amp.
500 IOUTA DAC IOUTB 225
Gain/Offset Adjust
The matching of the DAC output to the common-mode input of the AD8345 allows the two components to be dc-coupled, with no level shifting necessary. The combined voltage offset of the two parts can therefore be compensated for via the AD9777 programmable offset adjust. This allows excellent LO cancellation at the AD8345 output. The programmable gain adjust allows for optimal image rejection as well. The AD9777 evaluation board includes an AD8345 and recommended interface (Figure 105 and Figure 106). On the output of the AD9777, R9 and R10 convert the DAC output current to a voltage. R16 may be used to do a slight commonmode shift if necessary. The (now voltage) signal is applied to a low-pass reconstruction filter to reject DAC images. The components installed on the AD9777 provide a 35 MHz cutoff but may be changed to fit the application. A balun (MiniCircuits ADTL1-12) is used to cross the ground plane boundary to the AD8345. Another balun (Mini-Circuits ETC1-1-13) is used to couple the LO input of the AD8345. The interface requires a low ac impedance return path from the AD8345, therefore a single connection between the AD9777 and AD8345 ground planes is recommended. The performance of the AD9777 and AD8345 in an image reject transmitter, reconstructing three WCDMA carriers, can be seen in Figure 100. The LO of the AD8345 in this application is 800 MHz. Image rejection (50 dB) and LO feedthrough (-78 dBFS) have been optimized with the programmable features of the AD9777. The average output power of the digital waveform for this test was set to -15 dBFS to account for the peak-to-average ratio of the WCDMA signal.
0 -10 -20
AD8021
COPT 25 25 225 500 ROPT 225
02706-B-099
AVDD
Figure 99. Op Amp-Coupled Output Circuit
The common-mode (and second-order distortion) rejection of this configuration is typically determined by the resistor matching. The op amp used must operate from a dual supply since its output is approximately 1.0 V. A high speed amplifier, such as the AD8021, capable of preserving the differential performance of the AD9777 while meeting other system level objectives (i.e., cost, power) is recommended. The op amp's differential gain, gain setting resistor values, and full-scale output swing capabilities should all be considered when optimizing this circuit. ROPT is necessary only if level shifting is required on the op amp output. In Figure 99, AVDD, which is the positive analog supply for both the AD9777 and the op amp, is also used to level shift the differential output of the AD9777 to midsupply (i.e., AVDD/2).
INTERFACING THE AD9777 WITH THE AD8345 QUADRATURE MODULATOR
The AD9777 architecture was defined to operate in a transmit signal chain using an image reject architecture. A quadrature modulator is also required in this application and should be designed to meet the output characteristics of the DAC as much as possible. The AD8345 from Analog Devices meets many of the requirements for interfacing with the AD9777. As with any DAC output interface, there are a number of issues that have to be resolved. Among the major issues are the following.
AMPLITUDE (dBm)
-30 -40 -50 -60 -70 -80 -90
02706-B-100
-100 762.5
782.5
802.5 FREQUENCY (MHz)
822.5
842.5
DAC Compliance Voltage/Input Common-Mode Range
The dynamic range of the AD9777 is optimal when the DAC outputs swing between 1.0 V. The input common-mode range of the AD8345, at 0.7 V, allows optimum dynamic range to be achieved in both components.
Figure 100. AD9777/AD8345 Synthesizing a Three-Carrier WCDMA Signal at an LO of 800 MHz
Rev. B | Page 47 of 60
AD9777
EVALUATION BOARD
The AD9777 evaluation board allows easy configuration of the various modes, programmable via the SPI port. Software is available for programming the SPI port from Windows(R) 95, Windows 98, or Windows NT(R)/2000. The evaluation board also contains an AD8345 quadrature modulator and support circuitry that allows the user to optimally configure the AD9777 in an image reject transmit signal chain. Figure 101 to Figure 104 describe how to configure the evaluation board in the one-port and two-port input modes with the PLL enabled and disabled. Refer to Figure 105 to Figure 114, the schematics, and the layout for the AD9777 evaluation board for the jumper locations described below. The AD9777 outputs can be configured for various applications by referring to the following instructions.
DAC Differential Outputs
Transformers T2 and T3 should be in place. Note that the lower band of operation for these transformers is 300 kHz to 500 kHz. Jumpers 4, 8, 13 to 17, and 28 to 30 should remain unsoldered. The outputs are taken from S3 and S4.
Using the AD8345
Remove Transformers T2 and T3. Jumpers JP4 and 28 to 30 should remain unsoldered. Jumpers 13 to 16 should be soldered. The desired components for the low-pass interface filters L6, L7, C55, and C81 should be in place. The LO drive is connected to the AD8345 via J10 and the balun T4, and the AD8345 output is taken from J9.
DAC Single-Ended Outputs
Remove Transformers T2 and T3. Solder jumper link JP4 or JP28 to look at the DAC1 outputs. Solder jumper link JP29 or JP30 to look at the DAC2 outputs. Jumpers 8 and 13 to 17 should remain unsoldered. Jumpers JP35 to JP38 may be used to ground one of the DAC outputs while the other is measured single-ended. Optimum single-ended distortion performance is typically achieved in this manner. The outputs are taken from S3 and S4.
Rev. B | Page 48 of 60
AD9777
LECROY TRIG PULSE INP GENERATOR
SIGNAL GENERATOR
INPUT CLOCK AWG2021 OR DG2020 40-PIN RIBBON CABLE
DATACLK
CLK+/CLK-
DAC1, DB15-DB0 DAC2, DB15-DB0
AD9777
JUMPER CONFIGURATION FOR TWO PORT MODE PLL ON SOLDERED/IN x x x x x x x x x x x x
02706-B-101
UNSOLDERED/OUT x
JP1 - JP2 - JP3 - JP5 - JP6 - JP12 - JP24 - JP25 - JP26 - JP27 - JP31 - JP32 - JP33 -
Figure 101.1 Test Configuration for AD9777 in Two-Port Mode with PLL Enabled Signal Generator Frequency = Input Data Rate, DAC Output Data Rate = Signal Generator Frequency x Interpolation Rate2
LECROY TRIG PULSE INP GENERATOR
SIGNAL GENERATOR
INPUT CLOCK AWG2021 OR DG2020
ONEPORTCLK
CLK+/CLK-
DAC1, DB15-DB0 DAC2, DB15-DB0
AD9777
JUMPER CONFIGURATION FOR ONE PORT MODE PLL ON SOLDERED/IN x x x x x x x x
02706-B-102
UNSOLDERED/OUT x
JP1 - JP2 - JP3 - JP5 - JP6 - JP12 - JP24 - JP25 - JP26 - JP27 - JP31 - JP32 - JP33 -
x x x x
Figure 102.1 Test Configuration for AD9777 in One-Port Mode with PLL Enabled, Signal Generator Frequency = One-Half Interleaved Input Data Rate, ONEPORTCLK = Interleaved Input Data Rate, DAC Output Data Rate = Signal Generator Frequency x Interpolation Rate
1 2
To use PECL clock driver (U8), solder JP41 and JP42 and remove Transformer T1. In two-port mode, if DATACLK/PLL_LOCK is programmed to output Pin 8, JP25 and JP39 should be soldered. If DATACLK/PLL_LOCK is programmed to output Pin 53, JP46 and JP47 should be soldered. See the Two Port Data Input Mode section for more information.
Rev. B | Page 49 of 60
AD9777
LECROY TRIG PULSE INP GENERATOR
SIGNAL GENERATOR
INPUT CLOCK AWG2021 OR DG2020 40-PIN RIBBON CABLE
DATACLK
CLK+/CLK-
DAC1, DB15-DB0 DAC2, DB15-DB0
AD9777
JUMPER CONFIGURATION FOR TWO PORT MODE PLL OFF SOLDERED/IN x x x x x x x x x x x x
02706-B-103
UNSOLDERED/OUT x
JP1 - JP2 - JP3 - JP5 - JP6 - JP12 - JP24 - JP25 - JP26 - JP27 - JP31 - JP32 - JP33 -
Figure 103.1 Test Configuration for AD9777 in Two-Port Mode with PLL Disabled, DAC Output Data Rate = Signal Generator Frequency, DATACLK = Signal Generator Frequency/Interpolation Rate2
LECROY TRIG PULSE INP GENERATOR
SIGNAL GENERATOR
INPUT CLOCK AWG2021 OR DG2020
ONEPORTCLK
CLK+/CLK-
DAC1, DB15-DB0 DAC2, DB15-DB0
AD9777
JUMPER CONFIGURATION FOR ONE PORT MODE PLL OFF SOLDERED/IN x x x x x x x x
02706-B-104
UNSOLDERED/OUT x
JP1 - JP2 - JP3 - JP5 - JP6 - JP12 - JP24 - JP25 - JP26 - JP27 - JP31 - JP32 - JP33 -
x x x x
Figure 104.1 Test Configuration for AD9777 in One-Port Mode with PLL Disabled, DAC Output Data Rate = Signal Generator Frequency, ONEPORTCLK = Interleaved Input Data Rate = 2x Signal Generator Frequency/Interpolation Rate.
1 2
To use PECL clock driver (U8), solder JP41 and JP42 and remove Transformer T1. In two-port mode, if DATACLK/PLL_LOCK is programmed to output Pin 8, JP25 and JP39 should be soldered. If DATACLK/PLL_LOCK is programmed to output Pin 53, JP46 and JP47 should be soldered. See the Two Port Data Input Mode section for more information.
Rev. B | Page 50 of 60
L6 DNP R32 51
RC0603 CC0603
C79 DNP POWER INPUT FILTERS
O2N
LC0805 CC0805
C55 DNP
CC0805
C81 DNP JP19
RC0603 RC0603 LC0805
O2P W11
LC1210
VDDMIN
L8 FERRITE VDDM JP45
CC0805
L7 DNP 1 3 P
DCASE
R33 51 MODULATED OUTPUT C74 100pF DGND2; 3, 4, 5 J9
CC0603 RC0603
R34 DNP + C28 16V 22F 2
ADTL1-12
T5 S 4 R23 0 W12 2 DGND2
C32 0.1F
JP43
JP44
VDDM
6
BCASE
CC0603
C35 100pF CC0603
16 15 14 13 12 11 10 9
C75 0.1F 2 J8 VDDM DVDD_IN
L3 FERRITE
LC1210
G3
G4B
G4A
VPS2
QBBP
QBBN
VOUT
G2
+ C72 10V 10F
DCASE
JP9
TP2 RED DVDD
2
AD8345
U2
VPS1 ENBL
RC0603
+ C65 16V 22F
CC0805
C67 0.1F
DCASE
+ C66 16V 22F
IBBP
IBBN
G1A
G1B
LOIN
LOIP
R26 1k J5 JP18 2
DGND TP3 BLK AVDD_IN L2 FERRITE JP10
1
2
3
4
5
6
7
8
C78 0.1F
CC0603
RC0603
ADTL1-12
C54 DNP C73 L5 DNP DNP
CC0805
CC0805
Figure 105. AD8345 Circuitry on AD9777 Evaluation Board
C76 100pF 3 ETC1-1-13 4 R30 DNP 2 J6 JP7 JP21 T6 P 1 R35 51
RC0603 CC0603 DCASE CC0603
Rev. B | Page 51 of 60
LOCAL OSC INPUT R28 DGND2; 3, 4, 5 0 J10 RC0603 J4 2
CC0603
LC1210
TP4 RED AVDD
DCASE
CC0805
S 1 C77 100pF T4 2 5
P
+ C64 16V 22F AGND
C68 0.1F
DCASE
+ C61 16V 22F TP5 BLK CLKVDD_IN 2 J3 L1 FERRITE
LC1210
4 6 S
JP11
TP6 RED CLKVDD
3 L4 DNP
LC0805
+ C63 16V 22F J7 CGND
c
CC0805
C69 0.1F
DCASE
C80 DNP
+ C62 16V 22F TP7 BLK
O1N R36 51
RC0603
JP20
RC0603
O1P
LC0805
R37 DNP
02706-B-105
AD9777
AD9777
R2 1k DVDD
RC0603
R3 1k CLKVDD
CC0805 CC0805 RC0603 CC0805 CC0805 CC0805 CC0805 CC0603
RC0603
C36 0.1F R9 51k
RC0603
C37 0.1F JP4 JP28 J37 3 J35 2 1 T1-1T C58 DNP JP13 JP15 JP16 JP14 AVDD JP36 JP38 C18
CC0805 CC0603 CC0603 CC0603
C38 0.1F R16 10k 0.1F 0.1F 0.1F
CC0603
C39
C40
C41
R10 51k C70 0.1F
JP8
CC0603
C12 C27
CC0603 BCASE CC0603 CC0603
C11 0.1F 1pF
1 80
C42 0.1F AVDD C20
CC0603 CC0603 CC0603 BCASE
C1 + 10F 6.3V 0.1F
c 2 79 78 77 76 75 73 72
CC0603 CC0603
RC0603
c
TP15 WHT JP22 6 1
RC0603
C13 0.1F C19 0.1F 0.1F C14
5 4 2 3 CLKP
3 4 5 6 7 74 c 9 8 10 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
RC1206
CC0603
JP1
JP23 CLKN
R1 200 0.1F
+ C2 10F 6.3V
T2 4 5 6
AGND; 3, 4, 5 OUT1 S3
RC1206
JP2 R38 10k C58 DNP
T1 T1-1T JP33 ADCLK JP39 DVDD C26
CC0603
R42 49.9k
CLKIN
11 12 13 14 15 16 17 18
S1 C57 DNP C59 DNP
BCASE
ACLKX JP24 74VCX86 CX3 U3 AD10 C17 0.1F DVDD C25
CC0603
c
CGND; 3, 4, 5 + C10 10F 6.3V 0.001F AD13 AD12 AD11 C15
BCASE
AD15 AD14
O1N O1P O2N O2P
12 11 DVDD; 14 DGND; 7 0.1F
19 20 21 22 23 24 25 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 40 41 26 27 28 29 30 31 32 33 34 35 36 37 38 39
JP25
JP29 + C3 10F 6.3V JP30
CX2 CX1
13
0.1F
RC0603
T3 TP11 WHT TP10 WHT TP9 WHT TP8 WHT 3 2 1 4 5 6
TP14 WHT
BCASE
+ C9 10F 6.3V 0.001F
AGND; 3, 4, 5 OUT 2 S4
JP12 R40 DVDD 5k DGND; 3, 4, 5 DATACLK S2 R5 49.9
RC0603
CC0605
AGND; 3, 4, 5
02706-B-106
CC0805
Figure 106. AD9777 Clock, Power Supplies, and Output Circuitry
AD09 AD08 AD07 AD06 AD05 AD04
CC0603
Rev. B | Page 52 of 60
C16 R6 0.1F 1k DVDD C24
CC0603 BCASE
JP3
C29 0.1F + C8 10F 6.3V 0.001F AD03 AD02 AD01 AD00
BCASE
R8 R7 1k 2k 0.01% 0.01% C4 + 10F 6.3V SPCSP SPCLK SPSDI SPSDO
R43 49.9k T1-1T JP17 R12 C70 51k 0.1F
RC0603 CC0603
R11 51k
RC0603
R17 10k
RC0603
JP5
DVDD
BD15 R39 1k JP32 BD13 BD12 DVDD C23
CC0603
JP27
BCASE
OPCLK_3 JP26
C5 + 10F 6.3V
DGND; 3, 4, 5
JP40
S6 + C7 BCASE 10F 6.3V 0.001F BD11 BD10 BD09 BD08 BD14 74VCX86 JP31 12 11 U4 13 DVDD; 14 DGND; 7
IQ
IQ
BD00 C21 BD01 CC0603 BD02 0.001F BD03 BD04 BD05
JP46 DVDD BD06 BD07 C22
CC0603
74VCX86 8 IQ U4
JP47 9 10 SPSDO
OPCLK JP34
VDDC1 VDDA6 VSSA10 LF VDDA5 VDDC2 VSSA9 VSSC1 VDDA4 CLKP CLKN VSSA8 VSSA7 VSSC2 DCLK-PLLL IOUT1P VSSD1 IOUT1N VDDD1 VSSA6 VSSA5 P1D15 IOUT2P P1D14 IOUT2N P1D13 VSSA4 P1D12 VSSA3 P1D11 VDDA3 P1D10 VSSD2 VSSA2 VDDD2 U1 VDDA2 P1D9 VSSA1 VDDA1 P1D8 FSADJ1 P1D7 FSADJ2 P1D6 REFOUT P1D5 P1D4 RESET VSSD3 SP-CSB SP-CLK VDDD3 SP-SDI P1D3 SP-SDO P1D2 P1D1 VSSD6 VDDD6 P1D0 P2D0 P2D15-IQSEL P2D14-OPCLK P2D1 P2D2 P2D13 P2D3 P2D12 P2D4 VSSD4 VDDD4 P2D5 P2D11 VSSD5 VDDD5 P2D10 P2D9 P2D6 P2D7 P2D8
OPCLK S5
AD9777+TSP
0.001F
C6 + 10F 6.3V
BCASE
DVDD; 14 DGND; 7
C45 0.01F
RCOM 1 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 RP7 10 DNP
R1 R2 R3 R4 R5 R6 R7 R8 R9 RCOM RP5 50 10 1
R1 R2 R3 R4 R5 R6 R7 R8 R9
DATA-A
2
1
AD15 CX1 2 DVDD; 14 AGND; 7 4 AD11 5 U3 AD10 AD09 AD08 AD07 CX2 AD06 AD05 AD04 AD03 AD02 AD01 AD00 4 5 74VCX86 U4 6 DVDD; 14 AGND; 7 9 10 74VCX86 U3 8 DVDD; 14 AGND; 7 74VCX86 6 DVDD; 14 AGND; 7 U3 3 AD14 AD13 AD12
1
74VCX86
DVDD
4 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
3
6
ACASE
8
C30 + 4.7F 6.3V
C33 0.1F
CC0805
10
12
14
16
18
CX3
20
22
24
26
28
DVDD
30
32
RP1 1 RP1 2 RP1 3 RP1 4 RP1 5 RP1 6 RP1 7 RP1 8 RP2 1 RP2 2 RP2 3 RP2 4 RP2 5 RP2 6 RP2 7 RP2 8
22 16 22 15 22 14 22 13 22 12 22 11 22 10 22 9 22 16 22 15 22 14 22 13 22 12 22 11 22 10 22 9
Figure 107. AD9777 Evaluation Board Input (A Channel) and Clock Buffer Circuitry
Rev. B | Page 53 of 60
1 2 3 4 5 6 7 8 9 10 RP6 1 2 3 4 5 6 7 8 9 10 50 RCOM RCOM R1 R2 R3 R4 R5 R6 R7 R8 R9 R1 R2 R3 R4 R5 R6 R7 R8 R9 RP8 DNP R15 220
RC1206
34
C31 + 4.7F 6.3V
ACASE
C34 0.1F
CC0805
36
38
40
RIBBON J1
ADCLK
4
DVDD
10
DVDD PRE PRE J Q5 OPCLK_2
11
3
J
1 2
Q9 CLK K CLR
15
OPCLK
1 Q6 2
74VCX86 U4 3
OPCLK_3 DVDD; 14 AGND; 7 74LCX112 U7
12 13
CLK K CLR
14
Q7
C52 + 4.7F 6.3V
ACASE
C53 0.1F
CC0805
74LCX112 U7
AGND; 8 DVDD; 16
02706-B-107
AD9777
AD9777
CLKVDD R14 200
c
CC805 RC0805 RC0805
C47 1nF
c
R21 DNP RC0805 R20 DNP
RC0805
RCOM R4 120 MC100EPT22 7 U8 JP41 R22 DNP
RC0805
R1 R2 R3 R4 R5 R6 R7 R8 R9 2 1
CC805
R1 R2 R3 R4 R5 R6 R7 R8 R9 2 3 4 5 6 7 8 9 RP9 10 DNP C46 0.1F JP42 CLKP CLKN
CLKVDD
DATA-B
1
3
4
5
6
7
8
9
RCOM RP12 10 50 1
2
1
RP3 22 1 RP3 22 RP3 22 RP3 22 RP3 22 RP3 22 11
CC805 ACASE
16 15
RC0805
BD15 BD14 BD13
c c
CC805
2 CGND; 5 CLKVDD; 8 C48 1nF
4
3
2 3 4 CLKDD 5 6 RP3 22 RP3 22 RP4 22 RP4 22 RP4 22 RP4 22 RP4 22 RP4 22 RP4 22 RP4 22 9 BD00 10 BD01 2 U5 74AC14 1 DGND; 7 DVDD; 14 4 3 U5 74AC14 13 U5 74AC14 DGND; 7 DVDD; 14 10 U5 DGND; 7 74AC14 DVDD; 14 6 U5 74AC14 SPCLK SPSDI SPSDO 1 U6 2 DGND; 7 74AC14 DVDD; 14 3 DVDD
+
ACASE
ACLKX
RC0805
R13 120
CLKVDD R24 DNP RC0805
c
6
5
14 13 12 BD10 BD09 BD08 BD07
c c
8 9
7
BD12 BD11
R18 200
10
12
11
MC100EPT22 3 6 U8 4 CLKVDD; 8 CGND; 5
14
13
7 8 1 2 3 4 5 6 7 8 11 BD02 12 BD03 13 BD04 14 BD05 15 BD06 16 9
10
+ C49 4.7F 6.3V C60 0.1F
16
15
18
17
20
19
22
21
24
23
26
25
28
27
30
29
12
R50 9k
RC0805
32
31
Figure 108. AD9777 Evaluation Board Input (B Channel) and SPI Port Circuitry
Rev. B | Page 54 of 60
1 2 3 4 5 6 7 8 9 10 RP11 1 2 3 4 5 6 7 8 9 10 RP10 50 RCOM DNP RCOM R1 R2 R3 R4 R5 R6 R7 R8 R9 R1 R2 R3 R4 R5 R6 R7 R8 R9 SPCSB U6 C43 4.7F CC805 6.3V C50 0.1F 5
34
33
36
35
38
37
11 DGND; 7 DVDD; 14 5 8 U5 DGND; 7 DVDD; 14 74AC14 DGND; 7 DVDD; 14 9
R48 9k
RC0805
40
39
SPI PORT P1 1 2 R45 9k
RC0805
RIBBON J2
3 4 5 6
13 U6
12 DGND; 7 74AC14 DVDD; 14 4 DGND; 7 74AC14 DVDD; 14 U6 DGND; 7 74AC14 DVDD; 14 6 11 U6 10 DGND; 7 74AC14 DVDD; 14 9 8 DVDD
+
ACASE
U6 DGND; 7 74AC14 DVDD; 14
C44 4.7F 6.3V
CC805
C51 0.1F
02706-B-108
AD9777
Figure 109. AD9777 Evaluation Board Components, Top Side
Figure 110. AD9777 Evaluation Board Components, Bottom Side
Rev. B | Page 55 of 60
02706-B-110
02706-B-109
AD9777
Figure 111. AD9777 Evaluation Board Layout, Layer One (Top)
Figure 112. AD9777 Evaluation Board Layout, Layer Two (Ground Plane)
Rev. B | Page 56 of 60
02706-B-112
02706-B-111
AD9777
Figure 113. AD9777 Evaluation Board Layout, Layer Three (Power Plane)
Figure 114. AD9777 Evaluation Board Layout, Layer Four (Bottom)
Rev. B | Page 57 of 60
02706-B-114
02706-B-113
AD9777 OUTLINE DIMENSIONS
0.75 0.60 0.45 SEATING PLANE 1.20 MAX
80 1
14.00 SQ 12.00 SQ
61 60 60 61 80 1
PIN 1
TOP VIEW (PINS DOWN)
BOTTOM VIEW
6.00 SQ
20 21 40
41
41 40 21
20
0.15 0.05 1.05 1.00 0.95 0.20 0.09 COPLANARITY 0.08 0.50 BSC 0.27 0.22 0.17
7 3.5 0 GAGE PLANE 0.25
COMPLIANT TO JEDEC STANDARDS MS-026-ADD-HD
Figure 115. 80-Lead Thin Plastic Quad Flat Package, Exposed Pad [TQFP/ED] (SV-80) Dimensions shown in millimeters
ORDERING GUIDE
Models AD9777BSV AD9777BSVRL AD9777-EB Temperature Range -40C to +85C -40C to +85C Package Description 80-Lead Thin Plastic Quad Flatpack (TQFP) 80-Lead Thin Plastic Quad Flatpack (TQFP) Evaluation Board Package Option SV-80 SV-80
Rev. B | Page 58 of 60
AD9777 NOTES
Rev. B | Page 59 of 60
AD9777 NOTES
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02706-0-6/04(B)
Rev. B | Page 60 of 60

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